利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

81 条记录 (耗时 0.024 秒)

    Semiconductor device and manufacturing method thereof
    1.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06518635B1

    公开(公告)日：2003-02-11

    申请号：US09610862

    申请日：2000-07-06

    申请人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Yuji Abe ,  Yasunori Tokuda

    发明人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Yuji Abe ,  Yasunori Tokuda

    IPC分类号： H01L27108

    CPC分类号： H01L29/517 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28167

    摘要： A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.

    摘要翻译： 本发明的主要目的是提供一种改进的半导体器件，以便能够降低沟道边缘处的栅极电场集中，抑制MOSFET操作期间阈值的降低并减少漏电流。 在半导体衬底上形成栅极绝缘膜。 栅电极形成在半导体衬底上，其间具有栅极绝缘膜。 栅极绝缘膜的介电常数在表面上不均匀。

    Nitride semiconductor device and method of manufacturing the same
    2.
    发明授权
    Nitride semiconductor device and method of manufacturing the same 有权
    氮化物半导体器件及其制造方法

    公开(公告)号：US07842962B2

    公开(公告)日：2010-11-30

    申请号：US11274422

    申请日：2005-11-16

    申请人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Yuji Abe

    发明人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Yuji Abe

    IPC分类号： H01L33/00

    CPC分类号： H01L21/28575 ,  H01L33/32 ,  H01L33/40

    摘要： A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.

    摘要翻译： P型电极材料设置在P型接触层的顶表面上。 P型电极材料由AuGa膜，Au膜，Pt膜和Au膜形成。 AuGa膜设置在P型接触层上。 Au膜设置在AuGa膜上。 Pt膜设置在Au膜上。 Au膜设置在Pt膜上。 由此，可以获得具有能够降低P型接触层与P型电极之间的接触电阻的P型电极的氮化物半导体器件。

    Method of manufacturing nitride semiconductor device
    3.
    发明授权
    Method of manufacturing nitride semiconductor device 有权
    氮化物半导体器件的制造方法

    公开(公告)号：US07378351B2

    公开(公告)日：2008-05-27

    申请号：US11143685

    申请日：2005-06-03

    申请人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Zempei Kawazu ,  Yuji Abe

    发明人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Zempei Kawazu ,  Yuji Abe

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/28575 ,  H01L21/30621 ,  H01L33/0075 ,  H01S5/32341

    摘要： A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the GaN substrate subjected to the above-mentioned polishing by using a gas mixture of chlorine and oxygen, and the step of forming an n-type electrode on the back surface of the GaN substrate subjected to the above-mentioned dry etching.

    摘要翻译： 氮化物半导体器件通过在GaN衬底主表面上形成氮化物半导体层形成步骤，抛光由上述氮化物半导体层形成的GaN衬底的背面的步骤，干法蚀刻 通过使用氯和氧的气体混合物进行上述抛光的GaN衬底的背面，以及在经受上述干蚀刻的GaN衬底的背面上形成n型电极的步骤。

    Nitride semiconductor device and method of manufacturing the same
    4.
    发明申请
    Nitride semiconductor device and method of manufacturing the same 有权
    氮化物半导体器件及其制造方法

    公开(公告)号：US20060108596A1

    公开(公告)日：2006-05-25

    申请号：US11274422

    申请日：2005-11-16

    申请人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Yuji Abe

    发明人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Yuji Abe

    IPC分类号： H01L33/00

    CPC分类号： H01L21/28575 ,  H01L33/32 ,  H01L33/40

    摘要： A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.

    摘要翻译： P型电极材料设置在P型接触层的顶表面上。 P型电极材料由AuGa膜，Au膜，Pt膜和Au膜形成。 AuGa膜设置在P型接触层上。 Au膜设置在AuGa膜上。 Pt膜设置在Au膜上。 Au膜设置在Pt膜上。 由此，可以获得具有能够降低P型接触层与P型电极之间的接触电阻的P型电极的氮化物半导体器件。

    Method of manufacturing nitride semiconductor device
    5.
    发明申请
    Method of manufacturing nitride semiconductor device 有权
    氮化物半导体器件的制造方法

    公开(公告)号：US20060003490A1

    公开(公告)日：2006-01-05

    申请号：US11143685

    申请日：2005-06-03

    申请人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Zempei Kawazu ,  Yuji Abe

    发明人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Kazushige Kawasaki ,  Zempei Kawazu ,  Yuji Abe

    IPC分类号： H01L21/44 ,  H01L21/48

    CPC分类号： H01L21/28575 ,  H01L21/30621 ,  H01L33/0075 ,  H01S5/32341

    摘要： A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the GaN substrate subjected to the above-mentioned polishing by using a gas mixture of chlorine and oxygen, and the step of forming an n-type electrode on the back surface of the GaN substrate subjected to the above-mentioned dry etching.

    摘要翻译： 氮化物半导体器件通过在GaN衬底主表面上形成氮化物半导体层形成步骤，抛光由上述氮化物半导体层形成的GaN衬底的背面的步骤，干法蚀刻 通过使用氯和氧的气体混合物进行上述抛光的GaN衬底的背面，以及在经受上述干蚀刻的GaN衬底的背面上形成n型电极的步骤。

    Semiconductor device with sidewall spacers and elevated source/drain region
    8.
    发明授权
    Semiconductor device with sidewall spacers and elevated source/drain region 失效
    具有侧壁间隔件和升高的源极/漏极区域的半导体器件

    公开(公告)号：US06617654B2

    公开(公告)日：2003-09-09

    申请号：US09955488

    申请日：2001-09-19

    申请人： Toshiyuki Oishi ,  Kohei Sugihara ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    发明人： Toshiyuki Oishi ,  Kohei Sugihara ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    IPC分类号： H01L2976

    CPC分类号： H01L29/66628 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7834

    摘要： Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.

    摘要翻译： 源区和漏区包括在衬底的表面上的外延硅膜的区域和衬底中的区域。 源极和漏极区域的结的深度与延伸区域的接合点的深度相同或更浅。 结果，即使侧壁层的厚度减小，由于与源极和漏极区域相比，杂质浓度较低的延伸区域的耗尽层是主要的，所以短沟道效应具有较小的效果。

    Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction
    9.
    发明授权
    Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction 失效
    制造场效应晶体管的方法，其中寄生电容的增加受缩小的限制

    公开(公告)号：US06624034B2

    公开(公告)日：2003-09-23

    申请号：US10173835

    申请日：2002-06-19

    申请人： Yuji Abe ,  Naruhisa Miura ,  Kohei Sugihara ,  Toshiyuki Oishi ,  Yasunori Tokuda

    发明人： Yuji Abe ,  Naruhisa Miura ,  Kohei Sugihara ,  Toshiyuki Oishi ,  Yasunori Tokuda

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66628

    摘要： A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the channel region, where the source and drain regions are to be formed, forming respective pn junctions only between the neighborhood of the side surface parts and the pocket injection regions.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底的半导体区域的表面上的沟道区上形成栅电极，所述沟道区在半导体衬底中具有深度; 在栅电极的相对侧上形成第一对侧壁间隔物; 形成升高的半导体层，每个升高的半导体层相对于沟道区域升高，在一对侧壁间隔物外侧的区域上，并且将形成第一导电类型的源极和漏极区域; 移除所述一对第一侧壁间隔件; 以及形成第二导电类型的一对口袋注入区域，在除去侧壁间隔物之后，在半导体衬底中产生比形成侧壁间隔物的区域更深的第二导电类型的掺杂剂杂质，该对 分别仅覆盖要形成源极和漏极区的沟道区的各个侧表面部分的附近的口腔注入区域，仅在侧表面部分的附近和口袋注入区域之间形成相应的pn结。