公开(公告)号：US07840744B2

公开(公告)日：2010-11-23

申请号：US11668725

申请日：2007-01-30

Applicant: Mark David Bellows ,  Kent Harold Haselhorst ,  John David Irish ,  David Alan Norgaard

Inventor： Mark David Bellows ,  Kent Harold Haselhorst ,  John David Irish ,  David Alan Norgaard

IPC: G06F12/00

CPC classification number: G06F13/1694

Abstract: In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.

Abstract translation: 在一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。 提供了许多其他方面。

公开(公告)号：US07660246B2

公开(公告)日：2010-02-09

申请号：US11733218

申请日：2007-04-10

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: G01R31/08

CPC classification number: H04L47/10 ,  H04L41/0896 ,  H04L43/0882 ,  H04L47/12 ,  H04L47/326

Abstract: A method and apparatus are provided for scaling an input bandwidth for bandwidth allocation technology. An original bandwidth count value of an input flow is received. A bandwidth scaler constant is provided and used for scaling the received original bandwidth count value to provide a scaled bandwidth value between zero and one. The scaled bandwidth value is stored and used for calculating a transmit probability for the input flow.

Abstract translation: 提供了一种用于缩放用于带宽分配技术的输入带宽的方法和装置。 接收输入流的原始带宽计数值。 提供带宽缩放器常数并用于缩放所接收的原始带宽计数值，以提供零和一之间的缩放带宽值。 缩放的带宽值被存储并用于计算输入流的发送概率。

公开(公告)号：US20090327562A1

公开(公告)日：2009-12-31

申请号：US12145761

申请日：2008-06-25

Applicant: Mark David Bellows ,  Brian Patrick Burgess ,  John Dennis Folkerts ,  Roger John Gravrok ,  Brian Gerard Holthaus ,  Murali N. Iyer ,  Christopher James Martin ,  Timothy Gerald Robeck ,  Dennis J. Spathis

Inventor： Mark David Bellows ,  Brian Patrick Burgess ,  John Dennis Folkerts ,  Roger John Gravrok ,  Brian Gerard Holthaus ,  Murali N. Iyer ,  Christopher James Martin ,  Timothy Gerald Robeck ,  Dennis J. Spathis

IPC: G06F13/00

CPC classification number: G06F13/4022

Abstract: A method and apparatus are provided for implementing bus interface calibration to improve bus interface initialization time in a system. Bus interface calibration is performed and average calibration values are saved. At bus interface initialization time, checking for saved calibration values is performed. The saved calibration values are used and tested. When the saved calibration values pass the test, then the saved calibration values are used for system operation without performing any training steps.

Abstract translation: 提供了一种用于实现总线接口校准以改善系统中的总线接口初始化时间的方法和装置。 执行总线接口校准，并保存平均校准值。 在总线接口初始化时，执行保存的校准值的检查。 保存的校准值被使用和测试。 当保存的校准值通过测试时，保存的校准值用于系统操作，而不执行任何训练步骤。

公开(公告)号：US07613873B2

公开(公告)日：2009-11-03

申请号：US12031080

申请日：2008-02-14

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F12/00

CPC classification number: G11C11/40603 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C2207/2254

Abstract: A memory system employs calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are deferred to periods where no calibrations are taking place. The number of deferred refreshes is also tracked such that the overall loss of refreshes is prevented.

Abstract translation: 存储系统采用校准来确保数据的精确传输。 在校准期间，可能会发生内存刷新; 然而，这些刷新可能会干扰校准流。 因此，为了减轻碰撞和干扰，刷新推迟到不进行校准的时期。 还跟踪延期刷新的数量，以防止整体的刷新损失。

公开(公告)号：US07487318B2

公开(公告)日：2009-02-03

申请号：US11851468

申请日：2007-09-07

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/161 ,  G06F13/1647

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract translation: 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07467277B2

公开(公告)日：2008-12-16

申请号：US11348879

申请日：2006-02-07

Applicant: Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

Inventor： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC: G06F13/14

CPC classification number: G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract translation: 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US20080183985A1

公开(公告)日：2008-07-31

申请号：US11668725

申请日：2007-01-30

Applicant: Mark David Bellows ,  Kent Harold Haselhorst ,  John David Irish ,  David Alan Norgaard

Inventor： Mark David Bellows ,  Kent Harold Haselhorst ,  John David Irish ,  David Alan Norgaard

IPC: G06F12/00

CPC classification number: G06F13/1694

Abstract: In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.

Abstract translation: 在一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。 提供了许多其他方面。

公开(公告)号：US20080168262A1

公开(公告)日：2008-07-10

申请号：US11620117

申请日：2007-01-05

Applicant: Mark David Bellows ,  John David Irish ,  David Alan Norgaard ,  Tolga Ozguner ,  Dorothy Marie Thelen

Inventor： Mark David Bellows ,  John David Irish ,  David Alan Norgaard ,  Tolga Ozguner ,  Dorothy Marie Thelen

IPC: G06F9/312

CPC classification number: G06F9/3004

Abstract: In a first aspect, a first method of controlling a non-functional operation on a memory of a computer system using software is provided. The first method includes the steps of (1) employing a processor to write bits of data to at least one register external to the processor, wherein the bits of data serve as control bits for the memory; and (2) applying the bits of data to respective pins of the memory so as to cause the non-functional operation to be performed on the memory. Numerous other aspects are provided.

Abstract translation: 在第一方面，提供了一种使用软件来控制计算机系统的存储器上的非功能操作的第一方法。 第一种方法包括以下步骤：（1）使用处理器将数据位写入到处理器外部的至少一个寄存器，其中数据位用作存储器的控制位; 以及（2）将数据位施加到存储器的相应引脚，以使得对存储器执行非功能性操作。 提供了许多其他方面。

公开(公告)号：US20080168206A1

公开(公告)日：2008-07-10

申请号：US11620110

申请日：2007-01-05

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

IPC: G06F13/14

CPC classification number: G06F13/4059

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.

Abstract translation: 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。 提供了许多其他方面。

公开(公告)号：US07321961B2

公开(公告)日：2008-01-22

申请号：US11008792

申请日：2004-12-09

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/1605

Abstract: A method and apparatus to avoid collisions between row activate and column read or column write commands is presented. A memory controller includes control logic, activate allowed logic, and last column counter logic. The control logic sends particular values to the activate allowed logic and the last column counter logic at the beginning of a read or write operation, such as a new command load value, a read count value, and a write count value. In turn, the control logic receives an activate allowed signal from the activate allowed logic, which indicates the times at which a new activate command may be issued. As a result, the memory controller allows an activate command to commence on “even” command cycles or anytime after the last outstanding column command has been issued.

Abstract translation: 提出了一种避免行激活和列读或列写命令之间冲突的方法和装置。 存储器控制器包括控制逻辑，激活允许的逻辑和最后的列计数器逻辑。 控制逻辑在读或写操作开始时将特定值发送到激活允许的逻辑和最后的列计数器逻辑，例如新的命令加载值，读取计数值和写入计数值。 反过来，控制逻辑从激活允许的逻辑接收激活允许的信号，其指示可以发出新的激活命令的时间。 结果，存储器控制器允许激活命令在“偶数”命令周期或在最后一个未完成的列命令发出之后的任何时间开始。