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    Methods for in-situ chamber clean utilized in an etching processing chamber
    1.
    发明授权
    Methods for in-situ chamber clean utilized in an etching processing chamber 有权
    在蚀刻处理室中利用原位室清洁的方法

    公开(公告)号：US09533332B2

    公开(公告)日：2017-01-03

    申请号：US13614365

    申请日：2012-09-13

    申请人： Noel Sun ,  Meihua Shen ,  Nicolas Gani ,  Chung Nang Liu ,  Radhika C. Mani

    发明人： Noel Sun ,  Meihua Shen ,  Nicolas Gani ,  Chung Nang Liu ,  Radhika C. Mani

    IPC分类号： B08B5/00 ,  B08B7/00 ,  B08B9/08 ,  C23C16/44 ,  H01J37/32

    CPC分类号： B08B5/00 ,  B08B7/0035 ,  C23C16/4405 ,  H01J37/32449 ,  H01J37/32862 ,  Y10S438/905

    摘要： Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.

    摘要翻译： 本发明的实施例包括用于半导体器件中用于栅极结构制造工艺的等离子体处理室的原位室干洗的方法。 在一个实施例中，一种用于原位室干洗的方法包括在不存在设置在其中的基板的情况下将包括至少含硼气体的第一清洁气体供应到处理室中，提供至少包含含卤素气体的第二清洁气体 在没有基板的情况下进入处理室，并且在没有基板的情况下将至少包含含氧气体的第三清洁气体供应到处理室中。

    Device and method for etching flash memory gate stacks comprising high-k dielectric
    3.
    发明授权
    Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
    用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法

    公开(公告)号：US07780862B2

    公开(公告)日：2010-08-24

    申请号：US11386054

    申请日：2006-03-21

    申请人： Meihua Shen ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    发明人： Meihua Shen ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32136 ,  H01L21/31116

    摘要： In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.

    摘要翻译： 在一个实施方式中，提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。 该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层，将晶片转移到第二室而不破坏真空，蚀刻第二室中的高k电介质层，以及从第二室转移晶片 室到第一等离子体室，而不破坏真空。 在第一室中以低阴极温度蚀刻下导电材料层。 在一个实施方案中，高k电介质蚀刻是使用高温阴极的等离子体蚀刻。 在另一个实施方案中，高k电介质蚀刻是反应离子蚀刻。

    METHODS OF TRIMMING AMORPHOUS CARBON FILM FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE
    5.
    发明申请
    METHODS OF TRIMMING AMORPHOUS CARBON FILM FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE 审中-公开
    用于形成基底上超薄结构的非晶碳膜的方法

    公开(公告)号：US20090004875A1

    公开(公告)日：2009-01-01

    申请号：US12163888

    申请日：2008-06-27

    申请人： Meihua Shen ,  Diana Xiaobing Ma ,  Wendy H. Yeh ,  Kenneth MacWilliams ,  Wei Liu ,  Thorsten B. Lill

    发明人： Meihua Shen ,  Diana Xiaobing Ma ,  Wendy H. Yeh ,  Kenneth MacWilliams ,  Wei Liu ,  Thorsten B. Lill

    IPC分类号： H01L21/308

    CPC分类号： H01L21/0337

    摘要： Methods for forming an ultra thin structure using a method that includes trimming a mask layer during an etching process are provided. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on an underlying layer, trimming the photoresist layer to a first predetermined critical dimension, etching the hardmask layer through openings defined by the trimmed photoresist layer, trimming the hardmask layer to a second predetermined critical dimension, and etching the underlying layer through openings defined by the trimmed hardmask layer.

    摘要翻译： 提供了使用包括在蚀刻处理期间修整掩模层的方法来形成超薄结构的方法。 本文描述的实施例可有利地用于在临界尺寸小于55nm及以上的衬底上制造亚微米结构。 在一个实施例中，在衬底上形成亚微米结构的方法可以包括提供具有设置在膜堆叠上的图案化光致抗蚀剂层进入蚀刻室的衬底，其中所述膜堆叠包括至少设置在下层上的硬掩模层， 将光致抗蚀剂层修剪到第一预定临界尺寸，通过由修剪的光致抗蚀剂层限定的开口蚀刻硬掩模层，将硬掩模层修剪到第二预定临界尺寸，以及通过由修剪的硬掩模层限定的开孔蚀刻下层。

    DEVICE AND METHOD FOR ETCHING FLASH MEMORY GATE STACKS COMPRISING HIGH-K DIELECTRIC
    7.
    发明申请
    DEVICE AND METHOD FOR ETCHING FLASH MEMORY GATE STACKS COMPRISING HIGH-K DIELECTRIC 审中-公开
    用于蚀刻包含高K电介质的闪存存储器栅极堆叠的装置和方法

    公开(公告)号：US20080011423A1

    公开(公告)日：2008-01-17

    申请号：US11777714

    申请日：2007-07-13

    申请人： MEIHUA SHEN ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    发明人： MEIHUA SHEN ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    IPC分类号： C23F1/00

    CPC分类号： H01L21/32136 ,  H01L21/31116

    摘要： In one implementation, a method for etching a flash memory high-k gate stack on a workpiece is provided which includes etching a conductive material layer in a low temperature plasma chamber and etching a high-k dielectric layer in a high temperature plasma chamber. The workpiece is transferred between the low temperature plasma chamber and the high temperature plasma chamber through a vacuum transfer chamber connecting the low temperature plasma chamber and the high temperature plasma chamber. In one embodiment, an integrated etch station for etching a high-k flash memory structure is provided, which includes an etch chamber configured for plasma etch processing of a conductive material layer connected via a transfer chamber to an etch chamber configured for plasma etch processing of a high-k dielectric layer.

    摘要翻译： 在一个实施方案中，提供了一种用于蚀刻工件上的闪存高k栅极堆叠的方法，其包括在低温等离子体室中蚀刻导电材料层并蚀刻高温等离子体室中的高k电介质层。 工件通过连接低温等离子体室和高温等离子体室的真空传送室在低温等离子体室和高温等离子体室之间传递。 在一个实施例中，提供了用于蚀刻高k闪速存储器结构的集成蚀刻站，其包括蚀刻室，其被配置用于经由传送室连接到导电材料层的等离子体蚀刻处理到蚀刻室，所述蚀刻室被配置用于等离子体蚀刻处理 高k电介质层。

    CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS
    8.
    发明申请
    CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS 审中-公开
    CMOS S / D SiGe器件与替代整合过程

    公开(公告)号：US20070284668A1

    公开(公告)日：2007-12-13

    申请号：US11739103

    申请日：2007-04-24

    申请人： Meihua Shen ,  Yonah Cho ,  Mark Kawaguchi ,  Faran Nouri ,  Diana Ma

    发明人： Meihua Shen ,  Yonah Cho ,  Mark Kawaguchi ,  Faran Nouri ,  Diana Ma

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/28044 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： A semiconductor device includes a substrate having regions filled with an additive that forms a source/drain for a MOS device, a gate dielectric layer deposited over the substrate, the gate dielectric layer electrically isolates the substrate from subsequently deposited layers, a gate electrode deposited over the gate dielectric layer, an oxide liner formed along laterally opposite sidewalls of the gate electrode, a nitride layer formed along the oxide liner extending above the gate electrode, and wherein the additive and the nitride layer enclose the gate electrode.

    摘要翻译： 半导体器件包括具有填充有添加剂的区域的衬底，其形成用于MOS器件的源极/漏极，沉积在衬底上的栅极电介质层，栅极介电层将衬底与随后沉积的层电隔离，栅极电极沉积在 栅极电介质层，沿着栅电极的横向相对的侧壁形成的氧化物衬垫，沿着在栅电极上方延伸的氧化物衬垫形成的氮化物层，并且其中添加剂和氮化物层包围栅电极。

    ETCHING OF SiO2 WITH HIGH SELECTIVITY TO Si3N4 AND ETCHING METAL OXIDES WITH HIGH SELECTIVITY TO SiO2 AT ELEVATED TEMPERATURES WITH BCl3 BASED ETCH CHEMISTRIES
    10.
    发明申请
    ETCHING OF SiO2 WITH HIGH SELECTIVITY TO Si3N4 AND ETCHING METAL OXIDES WITH HIGH SELECTIVITY TO SiO2 AT ELEVATED TEMPERATURES WITH BCl3 BASED ETCH CHEMISTRIES 有权
    对具有高选择性的Si 3 N 4的SiO 2和具有高选择性的金属氧化物的蚀刻在基于BCl3的蚀刻化学的高温下

    公开(公告)号：US20070249182A1

    公开(公告)日：2007-10-25

    申请号：US11736562

    申请日：2007-04-17

    申请人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

    发明人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

    IPC分类号： H01L21/302 ,  H01L21/31

    CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

    摘要翻译： 具有高K电介质层和含氧化物或氮化物的层的晶片在电感耦合等离子体处理室中被蚀刻，通过施加源功率以产生电感耦合等离子体，将包含BCl 3 >，将晶片的温度设置在100℃和350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。 具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中进行蚀刻，将包含BCl 3 3的气体引入室中，设定晶片的温度 在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。 在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCI 3，将晶片的温度设定在20℃至200℃之间，并以大于10:1的氧化物至氮化物选择性蚀刻晶片。