摘要:
A semiconductor memory device includes bank arrays, row decoders, column decoders, a timing control circuit and repeaters. The bank arrays are distributed in a core region of a substrate, and each bank array includes sub-array blocks and includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. Each row decoder is disposed adjacent each bank array in a first direction. Each column decoder is disposed adjacent each bank array in a second direction. The timing control circuit, which is disposed in a peripheral region of the substrate, generates a first control signal to control the word-lines and a second control signal to control the bit-lines in response to operation control signals. Each repeater is disposed adjacent each column decoder and each repeater transfers the first and second control signals to the sub-array blocks in the second direction.
摘要:
A liquid crystal display (LCD) capable of preventing spots from being generated by difference in brightness caused by variation in a gap between substrates is provided. The LCD includes a first pad unit positioned on an upper corner of a lower substrate, a second pad unit positioned on a lower corner of the lower substrate diagonally across from the first pad unit, an integrated circuit electrically connected to the first pad unit and the second pad unit, and dummy pads positioned on the other upper corner of the lower substrate. The dummy pads are substantially symmetrical with second pads included in the second pad unit thus helping maintain the gap between the substrates uniform.
摘要:
A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode. According to the data input/output circuit and the semiconductor memory device having the data input/output circuit, it can be readily determined whether a data inversion function is normally performed.
摘要:
Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.
摘要:
A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode. According to the data input/output circuit and the semiconductor memory device having the data input/output circuit, it can be readily determined whether a data inversion function is normally performed.
摘要:
A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is possible to reduce the size of a semiconductor chip.
摘要:
Provided is a circuit for setting an optimized condition of a semiconductor circuit including a fuse cut signal generator configured to generate a fuse cut signal in response to a first control signal, and a state setting circuit configured to generate an optimization signal in response to a plurality of state control signals and the fuse cut signal.
摘要:
Provided is a circuit for setting an optimized condition of a semiconductor circuit including a fuse cut signal generator configured to generate a fuse cut signal in response to a first control signal, and a state setting circuit configured to generate an optimization signal in response to a plurality of state control signals and the fuse cut signal.
摘要:
Provided is a data input circuit of a semiconductor memory device. The data input circuit includes: an input buffer that samples an external data signal in response to a data strobe signal and outputs a first-sampled signal; a first domain converter that samples the first-sampled signal in response to a first clock signal and outputs a second-sampled signal; and a second domain converter that samples the second-sampled signal in response to a second clock signal containing write command information.
摘要:
Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.