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公开(公告)号：US20250103531A1
公开(公告)日：2025-03-27
申请号：US18919179
申请日：2024-10-17
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US20250086051A1
公开(公告)日：2025-03-13
申请号：US18892991
申请日：2024-09-23
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely Tsern
IPC: G06F11/10 , G06F11/16 , G06F11/20 , G11C7/10 , G11C29/00 , G11C29/42 , G11C29/44 , G11C29/52 , H03M13/15
Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
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公开(公告)号：US20250077459A1
公开(公告)日：2025-03-06
申请号：US18892110
申请日：2024-09-20
Applicant: Rambus Inc.
Inventor： Steven C. WOO
IPC: G06F13/40 , G06N3/045 , H01L25/065
Abstract: Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.
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公开(公告)号：US20250077124A1
公开(公告)日：2025-03-06
申请号：US18882333
申请日：2024-09-11
Applicant: Rambus Inc.
Inventor： Michael Thomas Imel , Larry Arbuthnot , Charles J. Wilson
Abstract: A memory controller includes a request queue and associated logic for efficiently managing the request queue based on various timing constraints of the memory device. A single request queue for the memory device stores read and write requests spanning different banks of the memory device. In each memory controller cycle, selection logic may select both a row request and a column request (relating to a different bank than the row request) for issuing to the memory device based on a set of timing status bits. Following issuance of requests, the memory controller updates the queue to maintain the queued requests in a time-ordered, compressed sequence. The memory controller furthermore updates the timing status bits that are used by the selection logic to select requests from the queue based on a history of past memory requests.
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公开(公告)号：US20250069644A1
公开(公告)日：2025-02-27
申请号：US18882372
申请日：2024-09-11
Applicant: Rambus Inc.
Inventor： Jared L. ZERBE , Frederick A. WARE
Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
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Patent Agency Ranking
公开(公告)号：US12230350B2
公开(公告)日：2025-02-18
申请号：US18243054
申请日：2023-09-06
Applicant: Rambus Inc.
Inventor： Adrian E. Ong , Fan Ho
IPC: G11C29/00 , G11C11/401 , G11C11/408 , G11C29/02 , G11C29/04 , G11C29/12 , G11C29/44 , G11C29/48
Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.
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公开(公告)号：US12224748B2
公开(公告)日：2025-02-11
申请号：US18504032
申请日：2023-11-07
Applicant: Rambus Inc.
Inventor： Huy Nguyen
Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
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公开(公告)号：US20250036304A1
公开(公告)日：2025-01-30
申请号：US18786883
申请日：2024-07-29
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Dongyun Lee
IPC: G06F3/06
Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
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公开(公告)号：US20250028636A1
公开(公告)日：2025-01-23
申请号：US18794937
申请日：2024-08-05
Applicant: Rambus Inc.
Inventor： Taeksang SONG , Steven C. WOO , Torsten PARTSCH
IPC: G06F12/06 , G11C11/408
Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.
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公开(公告)号：US12205669B2
公开(公告)日：2025-01-21
申请号：US18513473
申请日：2023-11-17
Applicant: Rambus Inc.
Inventor： Christopher Haywood , David Wang
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
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