公开(公告)号：US20190003068A9

公开(公告)日：2019-01-03

申请号：US13699910

申请日：2011-05-24

申请人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, JR. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

发明人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, JR. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

IPC分类号： C25D3/38

摘要： A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature. The deposition composition comprises (a) a source of copper ions; (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof; (c) an organic disulfide compound; (d) a compound selected from the group consisting of a reaction product of benzyl chloride and hydroxyethyl polyethyleneimine, a quaternized dipyridyl compound, and a combination thereof; and (d) chloride ions.

公开(公告)号：US08349393B2

公开(公告)日：2013-01-08

申请号：US10902398

申请日：2004-07-29

申请人： Yung-Herng Yau ,  Thomas B. Richardson ,  Joseph A. Abys ,  Karl F. Wengenroth ,  Anthony Fiore ,  Chen Xu ,  Chonglun Fan ,  John Fudala

发明人： Yung-Herng Yau ,  Thomas B. Richardson ,  Joseph A. Abys ,  Karl F. Wengenroth ,  Anthony Fiore ,  Chen Xu ,  Chonglun Fan ,  John Fudala

IPC分类号： B05D5/00

CPC分类号： H05K1/09 ,  C09D1/00 ,  C23C18/16 ,  C23C18/1614 ,  C23C18/1616 ,  C23C18/1633 ,  C23C18/1683 ,  C23C18/1687 ,  C23C18/42 ,  C23C18/44 ,  C23C18/54 ,  C23C22/06 ,  C23C22/58 ,  C25D3/46 ,  C25D3/56 ,  C25D3/64 ,  H05K3/244 ,  H05K3/422 ,  H05K2203/0257 ,  H05K2203/073 ,  Y10S205/916

摘要： Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.

公开(公告)号：US10541140B2

公开(公告)日：2020-01-21

申请号：US13981974

申请日：2012-01-26

申请人： Thomas B. Richardson ,  Joseph A. Abys ,  Wenbo Shao ,  Chen Wang ,  Vincent Paneccasio, Jr. ,  Cai Wang ,  Xuan Lin ,  Theodore Antonellis

发明人： Thomas B. Richardson ,  Joseph A. Abys ,  Wenbo Shao ,  Chen Wang ,  Vincent Paneccasio, Jr. ,  Cai Wang ,  Xuan Lin ,  Theodore Antonellis

IPC分类号： H01L21/288 ,  C25D3/38 ,  C25D5/18 ,  H01L21/768 ,  C25D7/12 ,  C25D5/02

摘要： A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

公开(公告)号：US10221496B2

公开(公告)日：2019-03-05

申请号：US13699910

申请日：2011-05-24

申请人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, Jr. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

发明人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, Jr. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

IPC分类号： C25D5/02 ,  C25D3/38 ,  H01L21/288 ,  H01L21/768 ,  C25D7/12

摘要： A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature. The deposition composition comprises (a) a source of copper ions; (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof; (c) an organic disulfide compound; (d) a compound selected from the group consisting of a reaction product of benzyl chloride and hydroxyethyl polyethyleneimine, a quaternized dipyridyl compound, and a combination thereof; and (d) chloride ions.

公开(公告)号：US09212427B2

公开(公告)日：2015-12-15

申请号：US12445049

申请日：2007-10-09

申请人： Stefan Schäfer ,  Thomas B. Richardson

发明人： Stefan Schäfer ,  Thomas B. Richardson

IPC分类号： C25D3/56 ,  C25D3/48 ,  C25D3/46

CPC分类号： C25D3/46

摘要： The invention relates to a cyanide-free electrolyte composition for depositing a silver or silver alloy layer on a substrate as well as a method for depositing such layers with the help of said cyanide-free electrolyte composition. The electrolyte composition according to the invention comprises at least one silver ion source, a sulfonic acid and/or a sulfonic acid derivative, a wetting agent and a hydantoin. The silver or silver alloy layers deposited from such an electrolyte composition by means of the method according to the invention are dull and ductile.

摘要翻译： 本发明涉及一种用于在基板上沉积银或银合金层的无氰化物电解质组合物以及借助所述无氰化物电解质组合物沉积这些层的方法。 根据本发明的电解质组合物包含至少一种银离子源，磺酸和/或磺酸衍生物，润湿剂和乙内酰脲。 通过本发明的方法由这种电解质组合物沉积的银或银合金层是钝的和延性的。

公开(公告)号：US07713859B2

公开(公告)日：2010-05-11

申请号：US11463355

申请日：2006-08-09

申请人： Thomas B. Richardson ,  Marlies Kleinfeld ,  Christian Rietmann ,  Igor Zavarine ,  Ortrud Steinius ,  Yun Zhang ,  Joseph A. Abys

发明人： Thomas B. Richardson ,  Marlies Kleinfeld ,  Christian Rietmann ,  Igor Zavarine ,  Ortrud Steinius ,  Yun Zhang ,  Joseph A. Abys

IPC分类号： H01L33/62

CPC分类号： H01L21/2885 ,  C25D3/60 ,  C25D21/18 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/11462 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014

摘要： A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant; and supplying an external source of electrons to the electrolytic bath to deposit a Sn—Ag alloy onto the under bump metal structure.

摘要翻译： 一种用于在微电子器件的制造中在下凸块金属结构上形成焊料凸块的工艺，包括将下凸块金属结构暴露于包含Sn 2+离子源，Ag +离子源，硫脲化合物和/或 季铵表面活性剂; 并向电解槽提供外部电子源，以将Sn-Ag合金沉积到下凸块金属结构上。

公开(公告)号：US07670950B2

公开(公告)日：2010-03-02

申请号：US12185641

申请日：2008-08-04

申请人： Thomas B. Richardson ,  Yun Zhang ,  Chen Wang ,  Vincent Paneccasio, Jr. ,  Cai Wang ,  Xuan Lin ,  Richard Hurtubise ,  Joseph A. Abys

发明人： Thomas B. Richardson ,  Yun Zhang ,  Chen Wang ,  Vincent Paneccasio, Jr. ,  Cai Wang ,  Xuan Lin ,  Richard Hurtubise ,  Joseph A. Abys

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  C25D3/38 ,  C25D5/02 ,  C25D7/123 ,  H01L21/2885

摘要： A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions.

摘要翻译： 一种用于在半导体集成电路器件衬底中金属化穿硅通孔特征的方法，包括将半导体集成电路器件衬底浸入包含铜离子源，有机磺酸或无机酸或一种或多种有机物的电解铜沉积组合物中 选自偏振器和/或去偏振器的化合物以及氯离子。

公开(公告)号：US20090035940A1

公开(公告)日：2009-02-05

申请号：US12185641

申请日：2008-08-04

申请人： Thomas B. Richardson ,  Yun Zhang ,  Chen Wang ,  Vincent Paneccasio, JR. ,  Cai Wang ,  Xuan Lin ,  Richard Hurtubise ,  Joseph A. Abys

发明人： Thomas B. Richardson ,  Yun Zhang ,  Chen Wang ,  Vincent Paneccasio, JR. ,  Cai Wang ,  Xuan Lin ,  Richard Hurtubise ,  Joseph A. Abys

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  C25D3/38 ,  C25D5/02 ,  C25D7/123 ,  H01L21/2885

摘要： A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions.

摘要翻译： 一种用于在半导体集成电路器件衬底中金属化穿硅通孔特征的方法，包括将半导体集成电路器件衬底浸入包含铜离子源，有机磺酸或无机酸或一种或多种有机物的电解铜沉积组合物中 选自偏振器和/或去偏振器的化合物以及氯离子。

公开(公告)号：US20140120722A1

公开(公告)日：2014-05-01

申请号：US13981974

申请日：2012-01-26

申请人： Thomas B. Richardson ,  Joseph A. Abys ,  Wenbo Shao ,  Chen Wang ,  Vincent Paneccasio, JR. ,  Cai Wang ,  Xuan Lin ,  Theodore Antonellis

发明人： Thomas B. Richardson ,  Joseph A. Abys ,  Wenbo Shao ,  Chen Wang ,  Vincent Paneccasio, JR. ,  Cai Wang ,  Xuan Lin ,  Theodore Antonellis

IPC分类号： H01L21/768

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D7/123 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76898

摘要： A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

摘要翻译： 一种用于在半导体集成电路器件中通过硅通孔特征进行金属化的工艺，该过程包括在填充周期期间使电路的极性反转一段间隔以在所述金属化衬底处产生阳极电位，并从铜表面解吸整齐器 通孔，然后通过重新建立通孔内的铜的表面作为电路中的阴极来恢复铜沉积，由此产生铜填充的通孔特征。

公开(公告)号：US20130199935A1

公开(公告)日：2013-08-08

申请号：US13699910

申请日：2011-05-24

申请人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, JR. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

发明人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, JR. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

IPC分类号： C25D3/38

CPC分类号： C25D3/38 ,  C25D5/02 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76898

摘要： A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature. The deposition composition comprises (a) a source of copper ions; (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof; (c) an organic disulfide compound; (d) a compound selected from the group consisting of a reaction product of benzyl chloride and hydroxyethyl polyethyleneimine, a quaternized dipyridyl compound, and a combination thereof; and (d) chloride ions.

摘要翻译： 一种用于在半导体集成电路器件衬底中金属化硅通孔特征的方法。 该方法包括将半导体集成电路器件衬底浸入电解铜沉积组合物中，其中贯穿硅通孔特征具有介于1微米至100微米之间的入口尺寸，20微米至750微米的深度尺寸，以及大于 约2：1; 向电解沉积组合物供给电流以将铜金属沉积到底部和侧壁上以进行自底向上填充，由此产生铜填充的通孔特征。 沉积组合物包含（a）铜离子源; （b）选自无机酸，有机磺酸及其混合物的酸; （c）有机二硫化物; （d）选自苄基氯和羟乙基亚乙基亚胺的反应产物，季铵化吡啶基化合物及其组合的化合物; 和（d）氯离子。