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    Magnetic random access memory device and method of forming the same
    2.
    发明申请
    Magnetic random access memory device and method of forming the same 有权
    磁性随机存取存储器件及其形成方法

    公开(公告)号：US20060174473A1

    公开(公告)日：2006-08-10

    申请号：US11347280

    申请日：2006-02-06

    申请人： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    发明人： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    IPC分类号： G11B5/33 ,  G11B5/127 ,  H04R31/00

    CPC分类号： G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

    摘要： Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

    摘要翻译： 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

    Magnetic random access memory device and method of forming the same
    4.
    发明申请
    Magnetic random access memory device and method of forming the same 有权

    公开(公告)号：US20080153179A1

    公开(公告)日：2008-06-26

    申请号：US12073098

    申请日：2008-02-29

    申请人： Se-Chung OH ,  Jang-Eun LEE ,  Jun-Soo BAE ,  Hyun-Jo KIM ,  Kyung-Tae NAM ,  Young-Ki HA

    发明人： Se-Chung OH ,  Jang-Eun LEE ,  Jun-Soo BAE ,  Hyun-Jo KIM ,  Kyung-Tae NAM ,  Young-Ki HA

    IPC分类号： H01L21/00

    CPC分类号： G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

    摘要： Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

    Method of writing to MRAM devices
    8.
    发明申请
    Method of writing to MRAM devices 有权
    写入MRAM设备的方法

    公开(公告)号：US20060039190A1

    公开(公告)日：2006-02-23

    申请号：US11097495

    申请日：2005-04-01

    申请人： Hyun-Jo Kim ,  Jang-Eun Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Young-Ki Ha ,  Kyung-Tae Nam

    发明人： Hyun-Jo Kim ,  Jang-Eun Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Young-Ki Ha ,  Kyung-Tae Nam

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16

    摘要： A method of writing to magnetic random access memory (MRAM) devices is provided. The method includes preparing a digit line disposed on a semiconductor substrate, a bit line crossing over the digit line, and a magnetic tunnel junction (MTJ) interposed between the digit line and the bit line. The MTJ has a pinned layer, a tunneling insulating layer, and a synthetic anti-ferromagnetic (SAF) free layer which are sequentially stacked. In addition, the SAF free layer has a bottom free layer and a top free layer which are separated by an exchange spacer layer. An initial magnetization state of the MTJ is read and compared with a desired magnetization state. When the initial magnetization state is different from the desired magnetization state, a first write line pulse is applied to one of the digit line and the bit line, and a second write line pulse is applied to the other of the digit line and the bit line, thereby changing the magnetization state of the MTJ. The MTJ may be disposed at an angle equal to or greater than 0° and less than 90° to a line to which the second write line pulse is applied.

    摘要翻译： 提供了一种写入磁性随机存取存储器（MRAM）器件的方法。 该方法包括准备设置在半导体衬底上的数字线，与数字线交叉的位线以及置于数字线和位线之间的磁性隧道结（MTJ）。 MTJ具有钉扎层，隧道绝缘层和顺序层叠的合成反铁磁（SAF）层。 此外，SAF自由层具有由交换间隔层隔开的无底层和顶部自由层。 读取MTJ的初始磁化状态并与期望的磁化状态进行比较。 当初始磁化状态不同于期望的磁化状态时，第一写入线脉冲被施加到数字线和位线之一，并且第二写入线脉冲被施加到数字线和位线中的另一个 ，从而改变MTJ的磁化状态。 MTJ可以以与第二写入线脉冲施加的线等于或大于0°且小于90°的角度布置。

    CMOS gate electrode using selective growth and a fabrication method thereof
    9.
    发明授权
    CMOS gate electrode using selective growth and a fabrication method thereof 失效
    CMOS栅电极及其制造方法

    公开(公告)号：US06696328B2

    公开(公告)日：2004-02-24

    申请号：US10413387

    申请日：2003-04-15

    申请人： Hwa-sung Rhee ,  Geum-jong Bae ,  Sang-su Kim ,  Jung-il Lee ,  Young-ki Ha ,  Ki-chul Kim

    发明人： Hwa-sung Rhee ,  Geum-jong Bae ,  Sang-su Kim ,  Jung-il Lee ,  Young-ki Ha ,  Ki-chul Kim

    IPC分类号： H01L218238

    CPC分类号： H01L21/823842 ,  Y10S438/933

    摘要： A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

    摘要翻译： 一种使用选择性生长方法形成的CMOS栅电极及其制造方法，其中在CMOS栅电极中，在半导体衬底的PMOS区上形成多晶硅锗（poly-SiGe）的第一栅极图案， 从下层选择性地生长多晶硅的栅极图案。 尽管PMOS区上的第一栅极图案是由多晶硅形成的，但NMOS区域上的第二栅极图案的特性不会恶化，从而增加了CMOS晶体管的总体特性。