公开(公告)号：US12147366B2

公开(公告)日：2024-11-19

申请号：US17853812

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Tresidder ,  Benjamin Tsien

IPC: G06F13/40 ,  G06F1/26

Abstract: Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the physical layer.

公开(公告)号：US12052153B2

公开(公告)日：2024-07-30

申请号：US16118848

申请日：2018-08-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Thomas James Gibney ,  Michael J. Tresidder ,  Nat Barbiero

IPC: H04L43/0876 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  H04L41/0813

CPC classification number: H04L43/0876 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  H04L41/0813 ,  Y02D10/00

Abstract: Systems, apparatuses, and methods for enabling localized control of link states in a computing system are disclosed. A computing system includes at least a host processor, a communication fabric, one or more devices, one or more links, and a local link controller to monitor the one or more links. In various implementations, the local link controller detects and controls states of a link without requiring communication with, or intervention by, the host processor. In various implementations, this local control by the link controller includes control over the clock signals provided to the link. For example, the local link controller can directly control the frequency of a clock supplied to the link. In addition, in various implementations the link controller controls the power supplied to the link. For example, the link controller can control the voltage supplied to the link.

公开(公告)号：US20240004821A1

公开(公告)日：2024-01-04

申请号：US17853812

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Tresidder ,  Benjamin Tsien

IPC: G06F13/40 ,  G06F1/26

CPC classification number: G06F13/4004 ,  G06F1/26 ,  G06F2213/40

Abstract: Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the physical layer.

公开(公告)号：US11132327B2

公开(公告)日：2021-09-28

申请号：US16204751

申请日：2018-11-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael J. Tresidder ,  Yanfeng Wang ,  Shiqi Sun

IPC: G06F13/42 ,  G06F13/20

Abstract: A method and apparatus for physical layer bypass data transmission between physical coding sub-layers (PCS) includes encoding the data for transmission over a serial low-speed link. The data is transmitted from a first PCS via a serial connection over a serializer/deserializer (SERDES) transmission bypass path The data is received by a second PCS via a SERDES receive bypass path.

公开(公告)号：US10541841B1

公开(公告)日：2020-01-21

申请号：US16130791

申请日：2018-09-13

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Shiqi Sun ,  Michael J. Tresidder ,  Yanfeng Wang

IPC: H03H7/30 ,  H04L25/03 ,  H04L7/00 ,  H04L25/02

Abstract: Systems, apparatuses, and methods for performing transmit equalization at a target high speed are disclosed. A computing system includes at least a transmitter, receiver, and a communication channel connecting the transmitter and the receiver. The communication channel includes a plurality of lanes which are subdivided into a first subset of lanes and a second subset of lanes. During equalization training, the first subset of lanes operate at a first speed while the second subset of lanes operate at a second speed. The first speed is the desired target speed for operating the communication link while the second speed is a relatively low speed capable of reliably carrying data over a given lane prior to equalization training. The first subset of lanes are trained at the first speed while feedback is conveyed from the receiver to the transmitter using the second subset of lanes operating at the second speed.

公开(公告)号：US11693465B2

公开(公告)日：2023-07-04

申请号：US17150600

申请日：2021-01-15

Applicant: ADVANCED MICRO DEVICES INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yanfeng Wang ,  Michael J. Tresidder ,  Kevin M. Lepak ,  Larry David Hewitt ,  Noah Beck

IPC: G06F1/32

CPC classification number: G06F1/32

Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

公开(公告)号：US11283589B2

公开(公告)日：2022-03-22

申请号：US17128720

申请日：2020-12-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Varun Gupta ,  Milam Paraschou ,  Gerald R. Talbot ,  Gurunath Dollin ,  Damon Tohidi ,  Eric Ian Carpenter ,  Chad S. Gallun ,  Jeffrey Cooper ,  Hanwoo Cho ,  Thomas H. Likens, III ,  Scott F. Dow ,  Michael J. Tresidder

IPC: H04B17/00 ,  H04L7/04 ,  H04L7/00

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

公开(公告)号：US20210132675A1

公开(公告)日：2021-05-06

申请号：US17150600

申请日：2021-01-15

Applicant: ADVANCED MICRO DEVICES INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yanfeng Wang ,  Michael J. Tresidder ,  Kevin M. Lepak ,  Larry David Hewitt ,  Noah Beck

IPC: G06F1/32

Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

公开(公告)号：US10895901B1

公开(公告)日：2021-01-19

申请号：US16586817

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Yanfeng Wang ,  Michael J. Tresidder ,  Kevin M. Lepak ,  Larry David Hewitt ,  Noah Beck

IPC: G06F1/32

Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

公开(公告)号：US20240004822A1

公开(公告)日：2024-01-04

申请号：US17854490

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： George D. Azevedo ,  Peter Malcolm Barnes ,  Michael J. Tresidder

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/409 ,  G06F13/4221 ,  G06F15/7807

Abstract: Systems, apparatuses, and methods for automatic firmware provision of high speed serializer/deserializer (SERDES) links are disclosed. A system on chip (SoC) includes one or more microcontrollers, a programmable interconnect, a plurality of physical layer engines, and a plurality of SERDES lanes. The programmable interconnect and the plurality of SERDES lanes are able to support communication protocols for interfaces such as PCIE, SATA, Ethernet, and others. On bootup, the SoC receives a custom specification of how the plurality of SERDES lanes are to be configured. The one or more microcontrollers generate a mapping for the programmable interconnect based on the specification. The mapping is used to configure the programmable interconnect to match the specification. The result is the programmable interconnect connecting the plurality of SERDES lanes to the appropriate physical layer circuits to implement the desired configuration.