公开(公告)号：US10831700B2

公开(公告)日：2020-11-10

申请号：US16443660

申请日：2019-06-17

Applicant: Apple Inc.

Inventor： Daniel Wilson ,  Anand Dalal ,  Josh De Cesare

IPC: G06F15/173 ,  G06F13/42 ,  G06F1/3287 ,  G06F13/364

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

公开(公告)号：US20190370217A1

公开(公告)日：2019-12-05

申请号：US16443660

申请日：2019-06-17

Applicant: Apple Inc.

Inventor： Daniel Wilson ,  Anand Dalal ,  Josh De Cesare

IPC: G06F15/173 ,  G06F13/42 ,  G06F1/3287 ,  G06F13/364

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

公开(公告)号：US10324891B2

公开(公告)日：2019-06-18

申请号：US15818507

申请日：2017-11-20

Applicant: APPLE INC.

Inventor： Daniel Wilson ,  Anand Dalal ,  Josh De Cesare

IPC: G06F15/17 ,  G06F15/173 ,  G06F13/42 ,  G06F1/3287 ,  G06F13/364

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

公开(公告)号：US20180074573A1

公开(公告)日：2018-03-15

申请号：US15818507

申请日：2017-11-20

Applicant: APPLE INC.

Inventor： Daniel Wilson ,  Anand Dalal ,  Josh De Cesare

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F15/17362 ,  G06F1/3287 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

公开(公告)号：US09823733B2

公开(公告)日：2017-11-21

申请号：US15394565

申请日：2016-12-29

Applicant: APPLE INC.

Inventor： Daniel Wilson ,  Anand Dalal ,  Josh De Cesare

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F15/17362 ,  G06F1/3287 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

公开(公告)号：US20170139468A1

公开(公告)日：2017-05-18

申请号：US15394565

申请日：2016-12-29

Applicant: APPLE INC.

Inventor： Daniel Wilson ,  Anand Dalal ,  Josh De Cesare

IPC: G06F1/32 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F15/17362 ,  G06F1/3287 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: Methods and apparatus for managing connections be multiple internal integrated circuits (ICs) of for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter. Chip™ (HSIC) in are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved dining, synchronization, and power consumption.

公开(公告)号：US20130254563A1

公开(公告)日：2013-09-26

申请号：US13890694

申请日：2013-05-09

Applicant: Apple Inc.

Inventor： Michael Culbert ,  Keith Alan Cox ,  Brian Howard ,  Josh De Cesare ,  Richard Charles Williams ,  Dave Robbins Falkenburg ,  Daisie Iris Huang ,  Dave Radcliffe

IPC: G06F1/26

CPC classification number: G06F1/206 ,  G05D23/1934 ,  G05D23/24 ,  G06F1/10 ,  G06F1/20 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y10S706/90

Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).