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    Methods and apparatus for correcting out-of-order data transactions between processors
    2.
    发明授权
    Methods and apparatus for correcting out-of-order data transactions between processors 有权

    公开(公告)号：US11379278B2

    公开(公告)日：2022-07-05

    申请号：US17035499

    申请日：2020-09-28

    Applicant: Apple Inc.

    Inventor： Karan Sanghi ,  Saurabh Garg

    IPC: G06F9/54 ,  G06F9/46 ,  G06F1/329

    Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

    Methods and apparatus for correcting out-of-order data transactions between processors
    4.
    发明授权
    Methods and apparatus for correcting out-of-order data transactions between processors 有权

    公开(公告)号：US10789110B2

    公开(公告)日：2020-09-29

    申请号：US16179667

    申请日：2018-11-02

    Applicant: Apple Inc.

    Inventor： Karan Sanghi ,  Saurabh Garg

    IPC: G06F9/54 ,  G06F9/46 ,  G06F1/329

    Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

    Methods and apparatus for loading firmware on demand
    5.
    发明授权
    Methods and apparatus for loading firmware on demand 有权

    公开(公告)号：US10572390B2

    公开(公告)日：2020-02-25

    申请号：US15273413

    申请日：2016-09-22

    Applicant: Apple Inc.

    Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

    IPC: G06F9/44 ,  G06F12/1009 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14 ,  G06F3/06

    Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

    Methods and apparatus for providing access to peripheral sub-system registers
    6.
    发明授权
    Methods and apparatus for providing access to peripheral sub-system registers 有权

    公开(公告)号：US10551902B2

    公开(公告)日：2020-02-04

    申请号：US15647088

    申请日：2017-07-11

    Applicant: Apple Inc.

    Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

    IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/4401 ,  G06F13/42

    Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

    METHODS AND APPARATUS FOR SINGLE ENTITY BUFFER POOL MANAGEMENT
    8.
    发明申请
    METHODS AND APPARATUS FOR SINGLE ENTITY BUFFER POOL MANAGEMENT 审中-公开

    公开(公告)号：US20190303204A1

    公开(公告)日：2019-10-03

    申请号：US16144992

    申请日：2018-09-27

    Applicant: Apple Inc.

    Inventor： CAHYA ADIANSYAH MASPUTRA ,  Karan Sanghi ,  Mingzhe Zhang ,  Zeh-Chen Liu ,  Sandeep Nair

    IPC: G06F9/50 ,  G06F3/06

    Abstract: Methods and apparatus for efficient data transfer within a user space network stack. Unlike prior art monolithic networking stacks, the exemplary networking stack architecture described hereinafter includes various components that span multiple domains (both in-kernel, and non-kernel). For example, unlike traditional “socket” based communication, disclosed embodiments can transfer data directly between the kernel and user space domains. Direct transfer reduces the per-byte and per-packet costs relative to socket based communication. A user space networking stack is disclosed that enables extensible, cross-platform-capable, user space control of the networking protocol stack functionality. The user space networking stack facilitates tighter integration between the protocol layers (including TLS) and the application or daemon. Exemplary systems can support multiple networking protocol stack instances (including an in-kernel traditional network stack).

    METHODS AND APPARATUS FOR LOCKING AT LEAST A PORTION OF A SHARED MEMORY RESOURCE
    9.
    发明申请
    METHODS AND APPARATUS FOR LOCKING AT LEAST A PORTION OF A SHARED MEMORY RESOURCE 审中-公开

    公开(公告)号：US20190227944A1

    公开(公告)日：2019-07-25

    申请号：US16259957

    申请日：2019-01-28

    Applicant: Apple Inc.

    Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

    IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/14 ,  G06F8/61 ,  G06F1/24 ,  G06F13/42

    Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

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