公开(公告)号：US11764058B2

公开(公告)日：2023-09-19

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H10B12/00

CPC classification number: H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L21/02579 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/30

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

公开(公告)号：US11456301B2

公开(公告)日：2022-09-27

申请号：US16931154

申请日：2020-07-16

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Sanjeev Manhas ,  Satendra Kumar Gautam

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.

公开(公告)号：US11974423B2

公开(公告)日：2024-04-30

申请号：US17551903

申请日：2021-12-15

Applicant: Applied Materials, Inc.

Inventor： Fredrick Fishburn ,  Arvind Kumar ,  Sony Varghese

IPC: H10B12/00

CPC classification number: H10B12/05 ,  H10B12/03

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

公开(公告)号：US10727232B2

公开(公告)日：2020-07-28

申请号：US16243551

申请日：2019-01-09

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Sanjeev Manhas ,  Satendra Kumar Gautam

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.

公开(公告)号：US20240355929A1

公开(公告)日：2024-10-24

申请号：US18634109

申请日：2024-04-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Sanjeev Manhas ,  Imtiyaz Ahmad Khan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H10B12/00

CPC classification number: H01L29/78645 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/315 ,  H10B12/485

Abstract: A memory device including at least one transistor having a dual gate structure comprising a first gate metal and a second gate metal, wherein the first gate metal has a work function of less than 4.55 eV and the second gate metal has a work function greater than 4.55 eV. A method of forming the memory device is also provided.

公开(公告)号：US20230102558A1

公开(公告)日：2023-03-30

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

公开(公告)号：US20240306391A1

公开(公告)日：2024-09-12

申请号：US18597057

申请日：2024-03-06

Applicant: Applied Materials, Inc.

Inventor： Hao-Ling Tang ,  Arvind Kumar ,  Mahendra Pakala ,  Keith Tatseun Wong ,  Yi-Hsuan Hsiao ,  Dongqing Yang ,  Mark Conrad ,  Rio Soedibyo ,  Minrui Yu

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: Two-dimensional (2D) materials formed in very thin layers improve the operation of semiconductor devices. However, forming a contact on 2D material tends to damage and penetrate the 2D material. A relatively gentle etch process has been developed that is very selective to the 2D material and allows vertical holes to be etched down to the 2D material without damaging or penetrating the 2D material. A low-power deposition process forms a protective liner when performing the metal fill to further prevent damage to the 2D material when forming the metal contacts in the holes. These processes allow a vertical metal contact to be formed on a planar 2D material or a vertical sidewall contact be formed in a 3D NAND without damaging the 2D material. This increases the contact area, reduces the contact resistance, and improves the performance of the 2D material in the device.

公开(公告)号：US11264460B2

公开(公告)日：2022-03-01

申请号：US16519246

申请日：2019-07-23

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Sanjeev Manhas ,  Mahendra Pakala ,  Ellie Y. Yieh

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L27/11556 ,  H01L27/11582

Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.