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公开(公告)号：US20220319585A1
公开(公告)日：2022-10-06
申请号：US17218949
申请日：2021-03-31
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Munish Kumar , Ayush Kulshrestha , Rajiv Kumar Sisodia , Yew Keong Chong , Kumaraswamy Ramanathan , Edward Martin McCombs, JR.
IPC: G11C11/418 , G11C11/16
Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.
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公开(公告)号：US11200922B2
公开(公告)日：2021-12-14
申请号：US16725779
申请日：2019-12-23
Applicant: Arm Limited
Inventor： Sriram Thyagarajan , Andy Wangkun Chen , Yew Keong Chong , Munish Kumar
Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.
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公开(公告)号：US20230136348A1
公开(公告)日：2023-05-04
申请号：US17515258
申请日：2021-10-29
Applicant: Arm Limited
Inventor： Sriram Thyagarajan , Yew Keong Chong , Munish Kumar , Andy Wangkun Chen , Rajiv Kumar Sisodia
Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.
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公开(公告)号：US20220319586A1
公开(公告)日：2022-10-06
申请号：US17223950
申请日：2021-04-06
Applicant: Arm Limited
Inventor： Rajiv Kumar Sisodia , Andy Wangkun Chen , Sriram Thyagarajan , Yew Keong Chong , Ayush Kulshrestha , Munish Kumar
IPC: G11C11/418 , G11C11/412 , G11C11/419
Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.
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公开(公告)号：US20200219890A1
公开(公告)日：2020-07-09
申请号：US16244047
申请日：2019-01-09
Applicant: Arm Limited
Inventor： Yew Keong Chong , Sriram Thyagarajan , Munish Kumar
IPC: H01L27/11 , H01L27/02 , G11C11/418 , H01L23/528 , G11C11/419
Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.
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Patent Agency Ranking
公开(公告)号：US09997217B1
公开(公告)日：2018-06-12
申请号：US15477516
申请日：2017-04-03
Applicant: ARM Limited
Inventor： Ankur Goel , Munish Kumar , Nitin Jindal , Rahul Mathur , Shruti Aggarwal , Bikas Maiti , Yew Keong Chong
CPC classification number: G11C7/12 , G11C7/1096 , G11C11/4087 , G11C11/419
Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.
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公开(公告)号：US20250103129A1
公开(公告)日：2025-03-27
申请号：US18474400
申请日：2023-09-26
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan , Munish Kumar , Vivek Asthana , Andrew John Turner , Alex James Waugh
IPC: G06F1/3296 , G06F12/0815
Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.
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公开(公告)号：US20240219955A1
公开(公告)日：2024-07-04
申请号：US18091719
申请日：2022-12-30
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan , Akash Bangalore Srinivasa , Munish Kumar , Khushal Gelda , Akshay Kumar
CPC classification number: G06F1/10 , G06F1/06 , G06F11/3062
Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.
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公开(公告)号：US11631439B1
公开(公告)日：2023-04-18
申请号：US17515258
申请日：2021-10-29
Applicant: Arm Limited
Inventor： Sriram Thyagarajan , Yew Keong Chong , Munish Kumar , Andy Wangkun Chen , Rajiv Kumar Sisodia
Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.
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公开(公告)号：US12066855B2
公开(公告)日：2024-08-20
申请号：US18091719
申请日：2022-12-30
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan , Akash Bangalore Srinivasa , Munish Kumar , Khushal Gelda , Akshay Kumar
CPC classification number: G06F1/10 , G06F1/06 , G06F11/3062
Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.
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