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公开(公告)号：US20140298068A1
公开(公告)日：2014-10-02
申请号：US13854434
申请日：2013-04-01
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Stephen V. Kosonocky , Christopher Spence Oliver , Sudha Thiruvengadam , Carson D. Henrion
CPC classification number: G06F1/3287 , Y02D10/171
Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.
Abstract translation: 集成电路装置包括布置在第一功率域内的第一模块，设置在作为第一功率域的子域的第二功率域中的第二模块，第一功率门控逻辑和第二功率门控逻辑。 第一电源门控逻辑为第一模块生成第一虚拟电源。 第二电源门控逻辑由第一虚拟电源供电，用于为第二电源域产生第二虚拟电源。
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2.发明授权公开(公告)号：US09891271B2
公开(公告)日：2018-02-13
申请号：US13946107
申请日：2013-07-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Russell Schreiber , Joel Irby , Sudha Thiruvengadam , Carl Dietz
CPC classification number: G01R31/2884
Abstract: A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. When the power grid is not working properly, the output of the test module is a fixed logic signal that does not vary based on the power gated state of the one or more modules.
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3.发明授权公开(公告)号：US09639488B2
公开(公告)日：2017-05-02
申请号：US14310215
申请日：2014-06-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Gregory Sadowski , Sudha Thiruvengadam , Arun Iyer
CPC classification number: G06F13/38 , G06F1/00 , G06F1/04 , G06F1/10 , H04L7/0008
Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.
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公开(公告)号：US20150372802A1
公开(公告)日：2015-12-24
申请号：US14310215
申请日：2014-06-20
Applicant: Advanced Micro Devices, Inc
Inventor： Gregory Sadowski , Sudha Thiruvengadam , Arun Iyer
CPC classification number: G06F13/38 , G06F1/00 , G06F1/04 , G06F1/10 , H04L7/0008
Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.
Abstract translation: 描述了通过减少系统中的信号转换来降低源同步总线系统中的功耗的方法的实施例。 而不是发送时钟和数据有效的信号，只有有效的数据包的开始和结束被标记为时钟信号转换，或者仅发送对应于数据字的数量的多个时钟脉冲，或者只有时钟信号上的数字转换 被发送。 时钟信号转换可以包括时钟脉冲或专用时钟信号的上升沿或下降沿转换。
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Patent Agency Ranking
5.发明授权Predictive periodic synchronization using phase-locked loop digital ratio updates 有权使用锁相环数字比较更新的预测周期性同步公开(公告)号：US09143315B2
公开(公告)日：2015-09-22
申请号：US14064045
申请日：2013-10-25
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mark Buckler , Sudha Thiruvengadam
CPC classification number: H04L7/0331 , G06F1/12 , H03J1/005 , H03L7/00 , H04L7/0012
Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.
Abstract translation: 描述了实现方案和系统，使得能够将来自时钟控制器的更新直接发送到预测同步器以管理发射和接收时钟域之间的频率的即时变化，包括从锁相环电路接收接收和发送参考频率 从耦合到锁相环电路的控制器接收和发送恒定码，获得延时因子以适应发射和接收时钟域之间的相位检测，并使用时间延迟因子计算新的检测间隔和频率信息， 参考频率和常数码。
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公开(公告)号：US20150026407A1
公开(公告)日：2015-01-22
申请号：US13946125
申请日：2013-07-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Edward J. McLellan , Sudha Thiruvengadam , Douglas R. Beard , Carl D. Dietz , Stephen V. Kosonocky
IPC: G06F12/08
CPC classification number: G06F12/0864 , G06F1/3206 , G06F1/3275 , G06F12/0804 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14
Abstract: As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache.
Abstract translation: 当处理器进入选择的低功耗模式时，通过将存储在高速缓存中的数据写入存储器层次结构的其他级别来缓冲数据。 高速缓存的刷新允许减小高速缓存的大小，而不会在将减少的高速缓存位置处的数据写入存储器层次结构方面带来额外的性能损失。 因此，当高速缓存退出所选择的低功率模式时，通过将高速缓存的路数设置为最小数量，将其设置为最小大小。 响应于处理系统处的定义的事件，高速缓存控制器改变每组高速缓存的路数。
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公开(公告)号：US09405357B2
公开(公告)日：2016-08-02
申请号：US13854434
申请日：2013-04-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen V. Kosonocky , Christopher Spence Oliver , Sudha Thiruvengadam , Carson D. Henrion
CPC classification number: G06F1/3287 , Y02D10/171
Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.
Abstract translation: 集成电路装置包括布置在第一功率域内的第一模块，设置在作为第一功率域的子域的第二功率域中的第二模块，第一功率门控逻辑和第二功率选通逻辑。 第一电源门控逻辑为第一模块生成第一虚拟电源。 第二电源门控逻辑由第一虚拟电源供电，用于为第二电源域产生第二虚拟电源。
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公开(公告)号：US20150026406A1
公开(公告)日：2015-01-22
申请号：US13946120
申请日：2013-07-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Edward J. McLellan , Sudha Thiruvengadam , Douglas R. Beard , Carl D. Dietz , Stephen V. Kosonocky
IPC: G06F12/08
CPC classification number: G06F12/0864 , G06F1/3275 , G06F1/3287 , G06F9/4418 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
Abstract: A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache.
Abstract translation: 通过各种方式来调整处理系统的高速缓存的大小，使得每组高速缓存具有相同数量的方式。 高速缓存是集合关联缓存，其中每个集合包括多种方式。 响应于处理系统处的定义的事件，高速缓存控制器改变每组高速缓存的路数。 例如，响应于处理器核心指示其进入减少活动的时段，高速缓存控制器可以减少高速缓存的每组中可用的路数。
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9.发明申请TECHNIQUES AND CIRCUITS FOR TESTING A VIRTUAL POWER SUPPLY AT AN INTEGRATED CIRCUIT DEVICE 有权在集成电路设备中测试虚拟电源的技术和电路公开(公告)号：US20150022218A1
公开(公告)日：2015-01-22
申请号：US13946107
申请日：2013-07-19
Applicant: Advanced Micro devices, Inc.
Inventor： Russell Schreiber , Joel Irby , Sudha Thiruvengadam , Carl Dietz
IPC: G01R31/02
CPC classification number: G01R31/2884
Abstract: A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. When the power grid is not working properly, the output of the test module is a fixed logic signal that does not vary based on the power gated state of the one or more modules.
Abstract translation: 电力网通过虚拟电源信号向集成电路装置的一个或多个模块供电。 测试模块被配置为响应测试信号的断言，使得当电网正常工作并且不是电源门控时，测试模块的输出与虚拟电源匹配。 当电网不能正常工作时，测试模块的输出是固定的逻辑信号，它不会根据一个或多个模块的电源门控状态而变化。
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