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    Spin-on cap layer, and semiconductor device containing same
    2.
    发明授权
    Spin-on cap layer, and semiconductor device containing same 有权
    旋转盖层，以及包含其的半导体器件

    公开(公告)号：US06724069B2

    公开(公告)日：2004-04-20

    申请号：US09827160

    申请日：2001-04-05

    申请人： Timothy Joseph Dalton ,  Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Christy Sensenich Tyberg

    发明人： Timothy Joseph Dalton ,  Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Christy Sensenich Tyberg

    IPC分类号： H01L2358

    CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

    摘要翻译： 提供了一种用作Cu互连结构的CMP后盖的旋涂帽。 本发明的旋涂帽包括低k电介质（约3.5或更小）和至少一种添加剂。 本发明中使用的至少一种添加剂能够结合Cu离子，并且可溶于旋转的低k电介质。 本发明的旋涂帽还可以包括旋转低k（约3.5或更小）反应离子蚀刻（RIE）停止层。 包含低电介质加上至少添加和低k RIE停止层的双层的旋转盖是优选的。 注意，本发明的本发明的旋涂帽不会显着增加互连结构的有效介电常数，并且不会增加互连结构的制造的额外成本，因为单个沉积工具，即旋涂工具 ，被雇用。 此外，由于在旋涂帽中存在添加剂，所以Cu迁移基本上被最小化。

    Interconnect structure with precise conductor resistance and method to form same
    3.
    发明授权
    Interconnect structure with precise conductor resistance and method to form same 有权
    具有精确导体电阻的互连结构和形成相同的方法

    公开(公告)号：US06710450B2

    公开(公告)日：2004-03-23

    申请号：US09795430

    申请日：2001-02-28

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L23532

    CPC分类号： H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/76811 ,  H01L21/7684

    摘要： An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics. Covalent bonding is achieved by employing an organosilane having functional groups that are capable of bonding with the top and bottom dielectric layers.

    摘要翻译： 提供了包括旋涂电介质的图案化多层的互连结构及其制造方法。 互连结构包括形成在衬底的表面上的旋涂电介质的图案化多层。 旋涂电介质的图案化多层由底部低k电介质，掩埋蚀刻停止层和顶部低k电介质组成，其中底部和顶部低k电介质具有第一组成，所述掩埋蚀刻 停止层具有与第一组成不同的第二组成，并且掩埋蚀刻停止层共价键合到所述顶部和底部低k电介质。 互连结构还包括形成在旋涂电介质的图案化多层上的抛光停止层; 以及形成在旋涂电介质的图案化多层中的金属导电区域。 通过使用具有能够与顶部和底部电介质层结合的官能团的有机硅烷来实现共价键合。

    Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
    5.
    发明授权
    Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics 有权
    低k互连结构由多层旋涂多孔电介质组成

    公开(公告)号：US06716742B2

    公开(公告)日：2004-04-06

    申请号：US10292205

    申请日：2002-11-12

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L214763

    CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

    摘要翻译： 提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。 具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。 使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。 本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。 选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。

    Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer
    6.
    发明授权
    Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer 有权
    互连件包含由多孔掩埋蚀刻停止层隔开的第一和第二多孔低k电介质

    公开(公告)号：US06831366B2

    公开(公告)日：2004-12-14

    申请号：US10396274

    申请日：2003-03-25

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L2352

    CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

    摘要翻译： 提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。 具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。 使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。 本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。 选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。

    Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
    7.
    发明授权
    Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials 有权
    混合低k互连结构由2个旋涂电介质材料组成

    公开(公告)号：US06677680B2

    公开(公告)日：2004-01-13

    申请号：US09795429

    申请日：2001-02-28

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L2348

    CPC分类号： H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

    摘要： A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

    摘要翻译： 提供了一种双镶嵌型金属布线加上低k电介质互连结构，其中导电金属线和通孔内置于混合低k电介质中，该电介质包括两个具有不同原子组成的旋转电介质和至少一个 的两个旋转电介质是多孔的。 用于形成本发明的混合低k电介质的两个旋转电介质各自具有约2.6或更小的介电常数，优选混合结构的每个电介质具有约1.2至约2.2的k。 通过利用本发明的混合低k电介质，获得对金属线电阻（沟槽深度）的优异控制，而不增加成本。 这是在没有使用掩埋蚀刻停止层的情况下实现的，如果存在的话，它将在两个旋转电介质之间形成。 此外，混合低k电介质的旋转电介质具有明显不同的原子组成，使得能够使用底部纺丝电介质（即，通过电介质）控制导体电阻，作为用于上纺丝的固有蚀刻停止层 电介质（即线电介质）。

    Semiconductor recessed mask interconnect technology
    10.
    发明授权
    Semiconductor recessed mask interconnect technology 失效
    半导体凹陷掩模互连技术

    公开(公告)号：US06657305B1

    公开(公告)日：2003-12-02

    申请号：US09703734

    申请日：2000-11-01

    申请人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    发明人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    IPC分类号： H01L2348

    CPC分类号： H01L21/76829 ,  H01L21/76804 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field. The invention is particularly useful in the damascene type device structure in the art wherein adjacent conductors extend from a substrate through an interlevel dielectric material, connections are made in a trench, a diffusion barrier liner is provided in the interlevel dielectric material and masking is employed to protect the dielectric material between conductors during processing operations.

    摘要翻译： 为半导体器件提供金属加上低介电常数（低k）互连结构，其中由电介质隔开的表面中的相邻区域在亚250纳米范围内具有宽度和间距的尺寸，并且其中减小横向漏电流 相邻的金属线和比常规结构更低的有效介电常数是通过在后续处理操作中在约2-5纳米以下的位置处定位用于保护电介质的微分或掩模构件来实现的 ，要平坦化，会有较低电场的表面。 本发明特别适用于本领域的镶嵌型器件结构，其中相邻导体从衬底延伸通过层间电介质材料，在沟槽中形成连接，在层间电介质材料中提供扩散阻挡衬垫，并且使用掩模 在处理操作期间保护导体之间的电介质材料。