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公开(公告)号：US10775863B2
公开(公告)日：2020-09-15
申请号：US15949677
申请日：2018-04-10
Applicant: Apple Inc.
Inventor： Michael Culbert , Keith Alan Cox , Brian Howard , Josh de Cesare , Richard Charles Williams , Dave Robbins Falkenburg , Daisie Iris Huang , David Radcliffe
IPC: G06F1/26 , G06F1/329 , G06F1/20 , G06F1/3203 , G06F1/324 , G06F1/3296 , G05D23/19 , G05D23/24 , G06F1/10 , G08G1/16
Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).
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公开(公告)号：US20150338892A1
公开(公告)日：2015-11-26
申请号：US14697471
申请日：2015-04-27
Applicant: Apple Inc.
Inventor： Michael Culbert , Keith Alan Cox , Brian Howard , Josh de Cesare , Richard Charles Williams , Dave Robbins Falkenburg , Daisie Iris Huang , David Radcliffe
CPC classification number: G06F1/206 , G05D23/1934 , G05D23/24 , G06F1/10 , G06F1/20 , G06F1/26 , G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y10S706/90
Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).
Abstract translation: 管理数据处理系统工作状态的方法和装置。 本发明的至少一个实施例包括具有一个或多个传感器（例如物理传感器，例如转速表和热敏电阻以及诸如CPU负载的逻辑传感器）的数据处理系统，用于一个或多个部件（例如，处理器 ，风扇，硬盘驱动器，光盘驱动器），用于平衡各种目标（例如用户偏好，性能，功耗，热约束，声学噪声）的工作条件。 在一个示例中，处理器的时钟频率和核心电压被主动地管理以平衡性能和功耗（发热）而没有显着的延迟。 在一个示例中，主动地管理冷却风扇的速度以平衡冷却力和噪声（和/或功率消耗）。
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公开(公告)号：US20160209895A1
公开(公告)日：2016-07-21
申请号：US15073521
申请日：2016-03-17
Applicant: Apple Inc.
Inventor： Michael Culbert , Keith Alan Cox , Brian Howard , Josh de Cesare , Richard Charles Williams , Dave Robbins Falkenburg , Daisie Iris Huang , David Radcliffe
CPC classification number: G06F1/26 , G05D23/1934 , G05D23/24 , G06F1/10 , G06F1/20 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , G08G1/167 , Y02D10/126 , Y02D10/172 , Y10S706/90
Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).
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Patent Agency Ranking
4.发明授权公开(公告)号：US09535875B2
公开(公告)日：2017-01-03
申请号：US14046824
申请日：2013-10-04
Applicant: Apple Inc.
Inventor： Daniel Wilson , Anand Dalal , Josh de Cesare
IPC: G06F15/17 , G06F15/173 , G06F13/42 , G06F1/32
CPC classification number: G06F15/17362 , G06F1/3287 , G06F13/364 , G06F13/4282 , G06F13/4295 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.
Abstract translation: 用于管理例如高速内部设备接口的多个内部集成电路（IC）之间的连接的方法和装置。 公开了用于协调连接和断开事件的改进方案，和/或高速片上（HSIC）接口的暂停和恢复操作。 在一个示例性实施例中，公开了一种“设备”引用和“主机”引用的连接/断开过程，其提供改进的定时，同步和功率消耗。
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公开(公告)号：US09317090B2
公开(公告)日：2016-04-19
申请号：US14697471
申请日：2015-04-27
Applicant: Apple Inc.
Inventor： Michael Culbert , Keith Alan Cox , Brian Howard , Josh de Cesare , Richard Charles Williams , Dave Robbins Falkenburg , Daisie Iris Huang , David Radcliffe
CPC classification number: G06F1/206 , G05D23/1934 , G05D23/24 , G06F1/10 , G06F1/20 , G06F1/26 , G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y10S706/90
Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).
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6.发明授权Methods and apparatuses for controlling the temperature of a data processing system 有权用于控制数据处理系统的温度的方法和装置公开(公告)号：US09043627B2
公开(公告)日：2015-05-26
申请号：US13890694
申请日：2013-05-09
Applicant: Apple Inc.
Inventor： Michael Culbert , Keith Alan Cox , Brian Howard , Josh de Cesare , Richard Charles Williams , Dave Robbins Falkenburg , Daisie Iris Huang , David Radcliffe
CPC classification number: G06F1/206 , G05D23/1934 , G05D23/24 , G06F1/10 , G06F1/20 , G06F1/26 , G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y10S706/90
Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).
Abstract translation: 管理数据处理系统工作状态的方法和装置。 本发明的至少一个实施例包括具有一个或多个传感器（例如物理传感器，例如转速表和热敏电阻以及诸如CPU负载的逻辑传感器）的数据处理系统，用于一个或多个部件（例如，处理器 ，风扇，硬盘驱动器，光盘驱动器），用于平衡各种目标（例如用户偏好，性能，功耗，热约束，声学噪声）的工作条件。 在一个示例中，处理器的时钟频率和核心电压被主动地管理以平衡性能和功耗（发热）而没有显着的延迟。 在一个示例中，主动地管理冷却风扇的速度以平衡冷却力和噪声（和/或功率消耗）。
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公开(公告)号：US20180232023A1
公开(公告)日：2018-08-16
申请号：US15949677
申请日：2018-04-10
Applicant: Apple Inc.
Inventor： Michael Culbert , Keith Alan Cox , Brian Howard , Josh de Cesare , Richard Charles Williams , Dave Robbins Falkenburg , Daisie Iris Huang , David Radcliffe
CPC classification number: G06F1/26 , G05D23/1934 , G05D23/24 , G06F1/10 , G06F1/20 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , G08G1/167 , Y02D10/126 , Y02D10/172 , Y10S706/90
Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).
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8.发明申请公开(公告)号：US20140181469A1
公开(公告)日：2014-06-26
申请号：US14046824
申请日：2013-10-04
Applicant: Apple Inc.
Inventor： Daniel Wilson , Anand Dalal , Josh de Cesare
IPC: G06F15/173
CPC classification number: G06F15/17362 , G06F1/3287 , G06F13/364 , G06F13/4282 , G06F13/4295 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.
Abstract translation: 用于管理例如高速内部设备接口的多个内部集成电路（IC）之间的连接的方法和装置。 公开了用于协调连接和断开事件的改进方案，和/或高速片上（HSIC）接口的暂停和恢复操作。 在一个示例性实施例中，公开了一种“设备”引用和“主机”引用的连接/断开过程，其提供改进的定时，同步和功率消耗。
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