中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

70 records (took 0.032 seconds)

    Robust decoding of wireless LAN response packets
    2.
    发明授权
    Robust decoding of wireless LAN response packets 有权

    公开(公告)号：US09641654B2

    公开(公告)日：2017-05-02

    申请号：US14499606

    申请日：2014-09-29

    Applicant: Apple Inc.

    Inventor： Koby Vainapel ,  Yoel Boger ,  Gilad Kirshenberg ,  Micha Anholt

    IPC: H04L12/50 ,  H04L29/06

    CPC classification number: H04L69/28 ,  H04L1/1614 ,  H04L1/1685 ,  H04L69/22

    Abstract: Embodiments described herein relate to a system and method for improving a rate of success in receiving response packets, such as 802.11 Acknowledge (ACK), Block Acknowledge (BACK), and Clear-To-Send (CTS) packets. In one embodiment, a wireless device may transmit one or more first packets according to a wireless communication protocol, and may then receive a second packet. The wireless device may determine that the receiving follows the transmitting by a specific duration of time that is specified by the wireless communication protocol for a response packet to follow one or more communication packets to which it responds. Based at least in part on this determining, the wireless device may further determine that the second packet is a response packet responding to the one or more first packets, without decoding a portion of the second packet that identifies a packet type of the second packet.

    Calculation of analog memory cell readout parameters using code words stored over multiple memory dies
    3.
    发明授权
    Calculation of analog memory cell readout parameters using code words stored over multiple memory dies 有权
    使用存储在多个存储器管芯上的代码字来计算模拟存储器单元读出参数

    公开(公告)号：US09021334B2

    公开(公告)日：2015-04-28

    申请号：US13874995

    申请日：2013-05-01

    Applicant: Apple Inc.

    Inventor： Barak Baum ,  Tomer Ish-Shalom ,  Micha Anholt ,  Eyal Gurgi ,  Yoav Kasorla

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1076 ,  G11C7/14 ,  G11C11/5621 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42

    Abstract: A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count.

    Abstract translation: 一种方法包括在包括两个或多个存储器单元的存储器中，存储可由多个检验方程表示的纠错码（ECC）的代码字，使得代码字的第一部分被存储在 第一存储单元和码字的第二部分被存储在第二存储单元中。 识别仅对属于存储在第一存储器单元中的第一部分的代码字位操作的检验方程的子集。 从第一存储器单元检索代码字的第一部分，并且对所检索的代码字的第一部分不满足的所识别的子集中的检验方程的计数进行评估。 根据评估计数来设定用于从第一存储器单元读出的一个或多个读出参数。

    THRESHOLD ADJUSTMENT USING DATA VALUE BALANCING IN ANALOG MEMORY DEVICE
    4.
    发明申请
    THRESHOLD ADJUSTMENT USING DATA VALUE BALANCING IN ANALOG MEMORY DEVICE 有权
    在模拟存储器件中使用数据值平衡进行阈值调整

    公开(公告)号：US20140325310A1

    公开(公告)日：2014-10-30

    申请号：US13908041

    申请日：2013-06-03

    Applicant: Apple Inc.

    Inventor： Micha Anholt ,  Eyal Gurgi ,  Barak Baum ,  Moshe Neerman ,  Moti Teitel

    IPC: G06F11/10

    CPC classification number: G11C29/021 ,  G06F11/1072 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/00 ,  G11C29/028 ,  G11C29/42

    Abstract: A method, in a memory including multiple analog memory cells, includes segmenting a group of the memory cells into a common section and at least first and second dedicated sections. Each dedicated section corresponds to a read threshold that is used for reading a data page to be stored in the group. Data to be stored in the group is jointly balanced over a union of the common section and the first dedicated section, and over the union of the common section and the second dedicated section, to create a balanced page such that for each respective read threshold an equal number of memory cells will be programmed to assume programming levels that are separated by the read threshold. The balanced page is stored to the common and dedicated sections, and the read thresholds are adjusted based on detecting imbalance between data values in readout results of the balanced page.

    Abstract translation: 一种在包括多个模拟存储器单元的存储器中的方法包括将一组存储器单元分成公共部分和至少第一和第二专用部分。 每个专用部分对应于用于读取要存储在组中的数据页的读取阈值。 要存储在组中的数据通过公共部分和第一专用部分的并集，并且在公共部分和第二专用部分的联合之间共同平衡，以创建平衡页面，使得对于每个相应的读取阈值 相同数量的存储器单元将被编程为假设由读取阈值分开的编程电平。 平衡页面存储到公共和专用部分，并且基于检测平衡页面的读出结果中的数据值之间的不平衡来调整读取阈值。

    DATA SCRAMBLING IN MEMORY DEVICES USING COMBINED SEQUENCES
    5.
    发明申请
    DATA SCRAMBLING IN MEMORY DEVICES USING COMBINED SEQUENCES 审中-公开
    使用组合序列在存储器件中进行数据扫描

    公开(公告)号：US20140310534A1

    公开(公告)日：2014-10-16

    申请号：US13862549

    申请日：2013-04-15

    Applicant: APPLE INC.

    Inventor： Eyal Gurgi ,  Micha Anholt ,  Shai Ojalvo

    IPC: G06F12/14

    CPC classification number: G06F12/1408 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/202 ,  G06F2212/7205 ,  Y02D10/13

    Abstract: A method for data storage includes generating a first scrambling sequence and a second scrambling sequence that is different from the first scrambling sequence. A combined sequence, which is equal to a bit-wise XOR between the first and second scrambling sequences, is generated. Data is copied from a first location in a memory in which the data is scrambled using the first scrambling sequence, to a second location in the memory in which the data is to be scrambled using the second scrambling sequence, by reading the data from the first location, scrambling the read data using the combined sequence, and then storing the data in the second location.

    Abstract translation: 一种用于数据存储的方法包括产生与第一加扰序列不同的第一加扰序列和第二加扰序列。 产生等于第一和第二加扰序列之间的逐位XOR的组合序列。 通过从第一个数据读取数据，将数据从数据被加扰的存储器中的第一位置使用第一加扰序列复制到数据要使用第二加扰序列进行加扰的存储器中的第二位置 位置，使用组合序列加扰读取数据，然后将数据存储在第二位置。

    HIGH-PERFORMANCE ECC DECODER
    7.
    发明申请
    HIGH-PERFORMANCE ECC DECODER 审中-公开
    高性能ECC解码器

    公开(公告)号：US20140164884A1

    公开(公告)日：2014-06-12

    申请号：US14182802

    申请日：2014-02-18

    Applicant: Apple Inc.

    Inventor： Micha Anholt ,  Naftali Sommer ,  Gil Semo ,  Tal Inbar

    IPC: H03M13/15

    CPC classification number: G06F11/1076 ,  H03M13/03 ,  H03M13/1525 ,  H03M13/45 ,  H03M13/617

    Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

    Abstract translation: 用于纠错码（ECC）解码的方法包括从表示已经用ECC编码的数据的一组位产生综合征。 错误定位器多项式（ELP）是基于综合征产生的。 识别至少一些ELP根，并校正由这些根指示的错误。 可以通过应用向量空间中的比特向量操作来产生每个综合征。 通过使用向量空间的不同基础应用向量运算来产生每个综合征。 可以通过使用串行乘法器对ELP系数进行操作，在给定的场元件上评估ELP，其中每个串行乘法器执行乘法周期序列，并在每个周期中产生中间结果。 响应于检测至少一个中期结果，指示给定的元素不是ELP根，在完成序列之前终止乘法循环。

    CUBIC ROOT OF A GALOIS FIELD ELEMENT
    9.
    发明申请
    CUBIC ROOT OF A GALOIS FIELD ELEMENT 有权
    GALOIS场元素的CUBIC根

    公开(公告)号：US20160147504A1

    公开(公告)日：2016-05-26

    申请号：US14551110

    申请日：2014-11-24

    Applicant: APPLE INC.

    Inventor： Micha Anholt ,  Moti Teitel

    IPC: G06F7/552 ,  G06F7/72

    CPC classification number: G06F7/724 ,  G06F7/552 ,  G06F7/5525 ,  G06F2207/5526

    Abstract: A method includes receiving a first element of a Galois Field of order qm, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qm and an integer p, where p is a prime number which divides qm−1. The second element z is raised to a pth power to form a third element. If the third element equals the first element, the second element multiplied by a pth root of unity raised to a respective power selected from a set of integers between 0 and p−1 is output as at least one root of the first element.

    Abstract translation: 一种方法包括接收秩序q m的伽罗瓦域的第一元素，其中q是素数，m是正整数。 将第一元件升高到预定的功率以形成第二元件z，其中预定功率是qm和整数p的函数，其中p是除以qm-1的素数。 第二元件z升高到第p个功率以形成第三元件。 如果第三元素等于第一元素，则将第二元素乘以第p个单位根提升到从0和p-1之间的整数集合中选择的相应功率作为第一元素的至少一个根。

Patent Agency Ranking