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公开(公告)号：US20220334997A1
公开(公告)日：2022-10-20
申请号：US17337805
申请日：2021-06-03
Applicant: Apple Inc.
Inventor： Sergio Kolor , Sergio V. Tota , Tzach Zemer , Sagi Lahav , Jonathan M. Redshaw , Per H. Hammarlund , Eran Tamari , James Vash , Gaurav Garg
IPC: G06F13/40 , G06F15/173
Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.
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公开(公告)号：US20230350828A1
公开(公告)日：2023-11-02
申请号：US18309192
申请日：2023-04-28
Applicant: Apple Inc.
Inventor： Sergio Kolor , Sergio V. Tota , Tzach Zemer , Sagi Lahav , Jonathan M. Redshaw , Per H. Hammarlund , Eran Tamari , James Vash , Gaurav Garg , Lior Zimet , Harshavardhan Kaushikkar , Steven Fishwick , Steven R. Hutsell , Shawn M. Fukami
IPC: G06F15/173 , G06F13/40
CPC classification number: G06F13/4027 , G06F13/4022 , G06F15/17375 , G06F15/17381
Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.
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公开(公告)号：US20230053530A1
公开(公告)日：2023-02-23
申请号：US17821305
申请日：2022-08-22
Applicant: Apple Inc.
Inventor： Per H. Hammarlund , Eran Tamari , Lior Zimet , Sergio Kolor , Sergio V. Tota , Sagi Lahav , James Vash , Gaurav Garg , Jonathan M. Redshaw , Steven R. Hutsell , Harshavardhan Kaushikkar , Shawn M. Fukami
IPC: G06F15/173 , G06F15/78 , G06F13/16 , G06F13/40
Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.
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Patent Agency Ranking
公开(公告)号：US11941742B2
公开(公告)日：2024-03-26
申请号：US17808392
申请日：2022-06-23
Applicant: Apple Inc.
Inventor： Adam J. Smith , Sergio V. Tota , Christopher G. Martin , Yoong Chert Foo , Terence M. Potter , Max J. Batley
CPC classification number: G06T15/005 , G06F9/3887
Abstract: Techniques are disclosed relating to processor communications fabrics. In some embodiments, a processor includes multiple client circuitry and fabric circuitry that includes at least first and second instances of a tile. The tile may include: client inputs configured to interface with client circuits, tile inputs configured to interface with one or more other tile instances, and communication resources assignable to the client inputs and tile inputs. The communications resources may include: multiple internal links, client outputs configured to interface with client circuits, and tile outputs configured to interface with one or more other tile instances. Control circuitry may, in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle, based on priority information. The control circuitry may update priority information based on assignment results over multiple cycles.
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公开(公告)号：US11675722B2
公开(公告)日：2023-06-13
申请号：US17337805
申请日：2021-06-03
Applicant: Apple Inc.
Inventor： Sergio Kolor , Sergio V. Tota , Tzach Zemer , Sagi Lahav , Jonathan M. Redshaw , Per H. Hammarlund , Eran Tamari , James Vash , Gaurav Garg , Lior Zimet , Harshavardhan Kaushikkar , Steven Fishwick , Steven R. Hutsell , Shawn M. Fukami
IPC: G06F13/40 , G06F15/173
CPC classification number: G06F13/4027 , G06F13/4022 , G06F15/17375 , G06F15/17381
Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.
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公开(公告)号：US20250124643A1
公开(公告)日：2025-04-17
申请号：US18989970
申请日：2024-12-20
Applicant: Apple Inc.
Inventor： Adam J. Smith , Sergio V. Tota , Christopher G. Martin , Yoong Chert Foo , Terence M. Potter , Max J. Batley
Abstract: Techniques are disclosed relating to processor communications fabrics. In some embodiments, a processor includes multiple client circuitry and fabric circuitry that includes at least first and second instances of a tile. The tile may include: client inputs configured to interface with client circuits, tile inputs configured to interface with one or more other tile instances, and communication resources that include internal links and outputs. The communication resources may be assignable to the client inputs and output and may include resources to satisfy all requests, in a given cycle, from one or more non-stallable channels supported by the apparatus. The communication resources may also include additional resources allocable, in a given cycle, to one or more stallable channels supported by the apparatus. Control circuitry may, in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle, based on priority information. The control circuitry may update priority information based on assignment results.
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公开(公告)号：US12007895B2
公开(公告)日：2024-06-11
申请号：US17821305
申请日：2022-08-22
Applicant: Apple Inc.
Inventor： Per H. Hammarlund , Eran Tamari , Lior Zimet , Sergio Kolor , Sergio V. Tota , Sagi Lahav , James Vash , Gaurav Garg , Jonathan M. Redshaw , Steven R. Hutsell , Harshavardhan Kaushikkar , Shawn M. Fukami
IPC: G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/109 , G06F12/128 , G06F13/16 , G06F13/28 , G06F13/40 , G06F15/173 , G06F15/78
CPC classification number: G06F12/0831 , G06F12/0811 , G06F12/0815 , G06F12/109 , G06F12/128 , G06F13/161 , G06F13/1668 , G06F13/28 , G06F13/4068 , G06F15/17368 , G06F15/7807 , G06F2212/305 , G06F2212/657
Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.
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公开(公告)号：US20230419585A1
公开(公告)日：2023-12-28
申请号：US17808392
申请日：2022-06-23
Applicant: Apple Inc.
Inventor： Adam J. Smith , Sergio V. Tota , Christopher G. Martin , Yoong Chert Foo , Terence M. Potter , Max J. Batley
CPC classification number: G06T15/005 , G06F9/3887
Abstract: Techniques are disclosed relating to processor communications fabrics. In some embodiments, a processor includes multiple client circuitry and fabric circuitry that includes at least first and second instances of a tile. The tile may include: client inputs configured to interface with client circuits, tile inputs configured to interface with one or more other tile instances, and communication resources assignable to the client inputs and tile inputs. The communications resources may include: multiple internal links, client outputs configured to interface with client circuits, and tile outputs configured to interface with one or more other tile instances. Control circuitry may, in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle, based on priority information. The control circuitry may update priority information based on assignment results over multiple cycles.
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