公开(公告)号：US11462411B2

公开(公告)日：2022-10-04

申请号：US17242375

申请日：2021-04-28

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Keyvan Kashefizadeh ,  Xikun Wang ,  Anchuan Wang ,  Sanjay Natarajan ,  Sean M. Seutter ,  Dong Wu

IPC: H01L21/283 ,  H01L29/49 ,  H01L21/28 ,  H01L29/45

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

公开(公告)号：US11114320B2

公开(公告)日：2021-09-07

申请号：US16690988

申请日：2019-11-21

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Takashi Kuratomi ,  Avgerinos V. Gelatos ,  Xianmin Tang ,  Sanjay Natarajan ,  Keyvan Kashefizadeh ,  Zhebo Chen ,  Jianxin Lei ,  Shashank Sharma

IPC: H01L21/67 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L21/02

Abstract: Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

公开(公告)号：US11004687B2

公开(公告)日：2021-05-11

申请号：US16442797

申请日：2019-06-17

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Keyvan Kashefizadeh ,  Xikun Wang ,  Anchuan Wang ,  Sanjay Natarajan ,  Sean M. Seutter ,  Dong Wu

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/45 ,  H01L21/283

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

公开(公告)号：US20180144973A1

公开(公告)日：2018-05-24

申请号：US15800784

申请日：2017-11-01

Applicant: Applied Materials, Inc.

Inventor： Weifeng Ye ,  Jiang Lu ,  Feng Chen ,  Zhiyuan Wu ,  Kai Wu ,  Vikash Banthia ,  He Ren ,  Sang Ho Yu ,  Mei Chang ,  Feiyue Ma ,  Yu Lei ,  Keyvan Kashefizadeh ,  Kevin Moraes ,  Paul F. Ma ,  Hua Ai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7685 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: Methods to selectively deposit capping layers on a copper surface relative to a dielectric surface comprising separately the copper surface to a cobalt precursor gas and a tungsten precursor gas, each in a separate processing chamber. The copper surface and the dielectric surfaces can be substantially coplanar. The combined thickness of cobalt and tungsten capping films is in the range of about 2 Å to about 60 Å.