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    SYSTEM AND METHODS FOR DRAM CONTACT FORMATION
    2.
    发明申请
    SYSTEM AND METHODS FOR DRAM CONTACT FORMATION 有权

    公开(公告)号：US20220336469A1

    公开(公告)日：2022-10-20

    申请号：US17688602

    申请日：2022-03-07

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL ,  Fredrick FISHBURN ,  Byeong Chan LEE

    IPC: H01L27/108

    Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.

    VOID-FREE CONTACT TRENCH FILL IN GATE-ALL-AROUND FET ARCHTECTURE
    4.
    发明申请
    VOID-FREE CONTACT TRENCH FILL IN GATE-ALL-AROUND FET ARCHTECTURE 有权

    公开(公告)号：US20220384258A1

    公开(公告)日：2022-12-01

    申请号：US17728871

    申请日：2022-04-25

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL ,  Byeong Chan LEE ,  Benjamin COLOMBEAU

    IPC: H01L21/768 ,  H01L29/40 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L23/522

    Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

    GALLIUM INTRODUCTION FOR CAVITY SHAPING ENGINEERING FOR CMOS DEVICES
    5.
    发明申请
    GALLIUM INTRODUCTION FOR CAVITY SHAPING ENGINEERING FOR CMOS DEVICES 有权

    公开(公告)号：US20250149381A1

    公开(公告)日：2025-05-08

    申请号：US18910704

    申请日：2024-10-09

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL

    IPC: H01L21/768

    Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a contact trench forming process to form a contact trench in a dielectric layer formed over a semiconductor region, performing a dopant implanting process to implant dopants in a region of the semiconductor region in proximity to an exposed surface of the semiconductor region within the contact trench, subsequent to the dopant implanting process, performing a cavity shaping process to form a cavity in the exposed surface of the semiconductor region within the contact trench, performing a silicide forming process to form a cavity contact within the contact trench, and performing a metal filling process to form a contact plug in the contact trench.

    METAL TREATMENT ON METAL SILICIDE FOR CMOS DEVICES
    6.
    发明申请
    METAL TREATMENT ON METAL SILICIDE FOR CMOS DEVICES 有权

    公开(公告)号：US20250081569A1

    公开(公告)日：2025-03-06

    申请号：US18817419

    申请日：2024-08-28

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL ,  Avgerinos V. GELATOS

    IPC: H01L29/40 ,  H01L21/768 ,  H01L29/49

    Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structure having a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, the cavity shaping process comprising forming a first cavity in an exposed surface of the p-type semiconductor region, performing a first selective deposition process to form a first cavity contact, selectively in the first cavity, and performing a metal treatment process on the formed first cavity contact, to remove oxides at interfaces of the first cavity contact with the first cavity.

    CONTACT FORMATION PROCESS FOR CMOS DEVICES
    7.
    发明公开
    CONTACT FORMATION PROCESS FOR CMOS DEVICES 审中-公开

    公开(公告)号：US20240014075A1

    公开(公告)日：2024-01-11

    申请号：US18206042

    申请日：2023-06-05

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL ,  Lisa MCGILL ,  Amritha RAMMOHAN ,  Shashank SHARMA

    IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

    CPC classification number: H01L21/823871 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895

    Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the mask covers an exposed surface of the second semiconductor region within the second opening, performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening, performing a removal process to remove the mask, performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region, and performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region.

    CONTACT FORMATION PROCESS FOR CMOS DEVICES
    8.
    发明公开
    CONTACT FORMATION PROCESS FOR CMOS DEVICES 审中-公开

    公开(公告)号：US20230377997A1

    公开(公告)日：2023-11-23

    申请号：US18123783

    申请日：2023-03-20

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL ,  Balasubramanian PRANATHARTHIHARAN ,  Benjamin COLOMBEAU ,  Anchuan WANG

    IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/768

    CPC classification number: H01L21/823871 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76895

    Abstract: A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.

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