公开(公告)号：US11269773B2

公开(公告)日：2022-03-08

申请号：US16595863

申请日：2019-10-08

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Andrew John Turner

IPC: G06F9/52 ,  G06F9/30 ,  G06F15/78 ,  G06F13/42 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0815

Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.

公开(公告)号：US10949292B1

公开(公告)日：2021-03-16

申请号：US16594223

申请日：2019-10-07

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Michael Andrew Campbell ,  Alexander Alfred Hornung ,  Alex James Waugh ,  Klas Magnus Bruce ,  Richard Roy Grisenthwaite

IPC: G06F11/20 ,  G11C29/08 ,  G06F11/10 ,  G11C29/18 ,  G06F11/30

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

公开(公告)号：US10917198B2

公开(公告)日：2021-02-09

申请号：US16027864

申请日：2018-07-05

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Tushar P. Ringe

IPC: H04L29/08 ,  H04L1/16

Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

公开(公告)号：US10282297B2

公开(公告)日：2019-05-07

申请号：US15427320

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

Abstract: A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

公开(公告)号：US11314675B2

公开(公告)日：2022-04-26

申请号：US16659762

申请日：2019-10-22

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew David Tune ,  Daniel Adam Sara ,  Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F12/0888 ,  G06F12/0815

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

公开(公告)号：US10579526B2

公开(公告)日：2020-03-03

申请号：US15427410

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/16

Abstract: A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. The snoop request includes an indication as to whether the requested data is to be returned to the source node and when the at least one data value includes the requested data, the transmitting circuitry transmits a response to the source node including said requested data, in dependence on said indication.

公开(公告)号：US10185663B2

公开(公告)日：2019-01-22

申请号：US15427409

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Jamshed Jalal ,  Michael Filippo ,  Bruce James Mathewson ,  Phanindra Kumar Mannava

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0831 ,  G06F12/128

Abstract: A data processing apparatus is provided including a memory hierarchy having a plurality of cache levels including a forwarding cache level, at least one bypassed cache level, and a receiver cache level. The forwarding cache level forwards a data access request relating to a given data value to the receiver cache level, inhibiting the at least one bypassed cache level from responding to the data access request. The receiver cache level includes presence determination circuitry for performing a determination as to whether the given data value is present in the at least one bypassed cache level. In response to the determination indicating that the data value is present in the at least one bypassed cache level, one of the at least one bypassed cache level is made to respond to the data access request.

公开(公告)号：US11483260B2

公开(公告)日：2022-10-25

申请号：US17051028

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Phanindra Kumar Mannava ,  Dimitrios Kaseridis

IPC: H04L49/50 ,  G06F13/36 ,  H04L47/11 ,  H04L49/15 ,  H04L49/25

Abstract: An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

公开(公告)号：US11256623B2

公开(公告)日：2022-02-22

申请号：US15427459

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Michael Filippo ,  Paul Gilbert Meyer ,  Alex James Waugh ,  Geoffray Matthieu Lacourba

IPC: G06F12/0831 ,  G06F12/0808

Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

公开(公告)号：US11055250B2

公开(公告)日：2021-07-06

申请号：US16593127

申请日：2019-10-04

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Klas Magnus Bruce ,  Damien Guillaume Pierre Payet ,  Jamshed Jalal ,  Alex James Waugh

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16

Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.