公开(公告)号：US5651112A

公开(公告)日：1997-07-22

申请号：US605688

申请日：1996-02-22

申请人： Atsushi Matsuno ,  Masanori Naito ,  Hiroshi Kobayashi ,  Masanori Horie ,  Hideki Sato ,  Masayuki Tanji ,  Shigeaki Wada ,  Toshimasa Saika

发明人： Atsushi Matsuno ,  Masanori Naito ,  Hiroshi Kobayashi ,  Masanori Horie ,  Hideki Sato ,  Masayuki Tanji ,  Shigeaki Wada ,  Toshimasa Saika

IPC分类号： G06F11/28 ,  G06F11/20 ,  G06F11/32 ,  G06F11/34 ,  G06F11/00

CPC分类号： G06F11/3466 ,  G06F11/3495 ,  G06F11/20 ,  G06F11/323 ,  G06F11/3419 ,  G06F2201/88

摘要： An information processing system capable of performance measurement by the use of a small amount of mounted hardware. The information processing system having central processors installed therein comprises a control circuit, and a performance measurement validation register for specifying whether a performance measurement function is valid or invalid. In a case where the validity of the measurement function has been specified by the register, the control circuit operates one loop in a duplex configuration as a performance measurement facility. At this time, counter #1-counter #3 are used as counters for totalizing performance information. On the other hand, in a case where the invalidity of the measurement function has been specified, both loops in the duplex configuration are operated as the central processors. At this time, the counter #1-the counter #3 are used as timer counters for controlling buses.

摘要翻译： 一种能够通过使用少量安装的硬件进行性能测量的信息处理系统。 其中安装有中央处理器的信息处理系统包括控制电路和用于指定性能测量功能是有效还是无效的性能测量验证寄存器。 在由寄存器指定测量功能的有效性的情况下，控制电路以双工配置的一个环路作为性能测量设备进行操作。 此时，计数器＃1计数器＃3被用作累计性能信息的计数器。 另一方面，在指定了测量功能的无效的情况下，双工配置中的两个环路都作为中央处理器进行操作。 此时，计数器＃1-计数器＃3用作控制总线的定时器计数器。

公开(公告)号：US08223017B2

公开(公告)日：2012-07-17

申请号：US12274597

申请日：2008-11-20

申请人： Tetsuya Oketani ,  Masayuki Tanji ,  Masanobu Takeuchi ,  Yutaka Nishizaka

发明人： Tetsuya Oketani ,  Masayuki Tanji ,  Masanobu Takeuchi ,  Yutaka Nishizaka

IPC分类号： G08B13/00

CPC分类号： A47F3/001 ,  F21V23/0442 ,  F21W2131/405 ,  F21Y2103/10 ,  F21Y2115/10 ,  H05B33/0854 ,  H05B37/0227 ,  Y02B20/44

摘要： An object is to provide a control apparatus of a showcase in which appropriate illumination having a high presentation effect can be realized by an LED illumination apparatus having a high durability against turning ON/OFF and capable of securing a predetermined illumination intensity even under an environment at a low temperature. The control apparatus controls a plurality of showcases so that display chambers where commodities are displayed are illuminated with LED illumination apparatuses, and includes a person detecting sensor provided in a showcase disposed in such a position that the approaching of any person can first be detected among the plurality of arranged showcases, so that the approaching of the person is detected. When the person detecting sensor detects the approaching of the person, the illumination intensities of all the LED illumination apparatuses of the plurality of showcases are increased.

摘要翻译： 本发明的目的是提供一种展示柜的控制装置，其中具有高展现效果的适当的照明可以通过具有高的打开/关闭耐久性的LED照明装置来实现，并且即使在环境中也能够确保预定的照明强度 低温。 控制装置控制多个陈列柜，使得显示商品的显示室被LED照明装置照射，并且包括设置在陈列柜中的人物检测传感器，该陈列柜设置在可以首先被检测到的任何人的接近 多个布置的陈列柜，以便检测到人的接近。 当人检测传感器检测到人的接近时，多个陈列柜的所有LED照明装置的照明强度增加。

公开(公告)号：US20090135011A1

公开(公告)日：2009-05-28

申请号：US12274597

申请日：2008-11-20

申请人： Tetsuya Oketani ,  Masayuki Tanji ,  Masanobu Takeuchi ,  Yataka Nishizaka

发明人： Tetsuya Oketani ,  Masayuki Tanji ,  Masanobu Takeuchi ,  Yataka Nishizaka

IPC分类号： G08B5/00

CPC分类号： A47F3/001 ,  F21V23/0442 ,  F21W2131/405 ,  F21Y2103/10 ,  F21Y2115/10 ,  H05B33/0854 ,  H05B37/0227 ,  Y02B20/44

摘要： An object is to provide a control apparatus of a showcase in which appropriate illumination having a high presentation effect can be realized by an LED illumination apparatus having a high durability against turning ON/OFF and capable of securing a predetermined illumination intensity even under an environment at a low temperature. The control apparatus controls a plurality of showcases so that display chambers where commodities are displayed are illuminated with LED illumination apparatuses, and includes a person detecting sensor provided in a showcase disposed in such a position that the approaching of any person can first be detected among the plurality of arranged showcases, so that the approaching of the person is detected. When the person detecting sensor detects the approaching of the person, the illumination intensities of all the LED illumination apparatuses of the plurality of showcases are increased.

摘要翻译： 本发明的目的是提供一种展示柜的控制装置，其中具有高展现效果的适当的照明可以通过具有高的打开/关闭耐久性的LED照明装置来实现，并且即使在环境中也能够确保预定的照明强度 低温。 控制装置控制多个陈列柜，使得显示商品的显示室被LED照明装置照射，并且包括设置在陈列柜中的人物检测传感器，该陈列柜设置在可以首先被检测到的任何人的接近 多个布置的陈列柜，以便检测到人的接近。 当人物检测传感器检测到人的接近时，多个陈列柜的所有LED照明装置的照明强度增加。

公开(公告)号：US4764869A

公开(公告)日：1988-08-16

申请号：US900987

申请日：1986-08-27

申请人： Yoshihiro Miyazaki ,  Soichi Takaya ,  Masayuki Tanji ,  Atsuhiko Nishikawa ,  Shinichiro Yamaguchi

发明人： Yoshihiro Miyazaki ,  Soichi Takaya ,  Masayuki Tanji ,  Atsuhiko Nishikawa ,  Shinichiro Yamaguchi

IPC分类号： G06F9/46 ,  G06F9/48

CPC分类号： G06F9/4812

摘要： Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.

摘要翻译： 用于控制处理器中断的方法和装置。 当在执行指令的过程中检测到具有比当前程序级别更高的优先级的外部中断请求时，处理被中断，并且发出间歇中断。 在该中断中程序电平被固定，使得在中断目的地处理中断请求作为正常的中断请求，并且在中断处理之后的第二个返回指令处理从中断点恢复。

公开(公告)号：US5623626A

公开(公告)日：1997-04-22

申请号：US440692

申请日：1995-05-15

申请人： Michio Morioka ,  Tadaaki Bandoh ,  Masayuki Tanji

发明人： Michio Morioka ,  Tadaaki Bandoh ,  Masayuki Tanji

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1045

摘要： A logical cache memory has a logical tag and a physical tag as address tags for comparison, and status information representing their status. Data status and block status are registered at the same entry position. When access is made using a logical address, access is made to the logical tag to detect the existence of data, and when access is made using a physical address, access is made to the physical tag using an offset portion which does not depend on address conversion, to detect the existence of data.

摘要翻译： 逻辑高速缓存存储器具有逻辑标签和物理标签作为用于比较的地址标签，以及表示其状态的状态信息。 数据状态和块状态被登记在同一个入口位置。 当使用逻辑地址进行访问时，对逻辑标签进行访问以检测数据的存在，并且当使用物理地址进行访问时，使用不依赖于地址的偏移部分对物理标签进行访问 转换，检测数据的存在。

公开(公告)号：US5297290A

公开(公告)日：1994-03-22

申请号：US408731

申请日：1989-09-18

申请人： Koji Masui ,  Masayuki Tanji

发明人： Koji Masui ,  Masayuki Tanji

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F13/24 ,  G06F15/177 ,  G06F13/14 ,  G06F13/368

CPC分类号： G06F13/24

摘要： An interruption signal from a common input/output device is coupled to all processors through a common bus, and each processor issues to the common bus its own interruption receipt acceptance or negation state and the respective processors watch and decide individually interruption receipt acceptance or negation states on the common bus of the individual processors. Only one of processors which are ready to accept the receipt of interruption is allowed to accept the receipt of an interruption signal from the common input/output device in accordance with a predetermined priority.

摘要翻译： 来自公共输入/输出设备的中断信号通过公共总线耦合到所有处理器，并且每个处理器向公共总线发出其自己的中断接收接受或否定状态，并且各个处理器监视和决定单独的中断接收接收或否定状态 在各个处理器的公共总线上。 只有一个准备接受中断的接收的处理器被允许根据预定的优先级接受来自公共输入/输出设备的中断信号的接收。

公开(公告)号：US06216236B1

公开(公告)日：2001-04-10

申请号：US09188903

申请日：1998-11-10

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F1134

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。 每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。 三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障 （20-1,20-2,20-3）。 如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。 此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

公开(公告)号：US5901281A

公开(公告)日：1999-05-04

申请号：US434288

申请日：1995-05-03

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G11C29/00 ,  G06F11/34

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/184 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G06F11/1641 ,  G06F11/18 ,  G06F11/185 ,  G06F11/20 ,  G11C29/74

摘要： A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线连接的多个处理单元。 每个处理单元在公共支撑板（PL）上具有三个或更多个处理器，并由公共时钟单元控制。 三个处理器执行相同的操作，并且通过比较三个处理器的操作来检测处理器中的故障。 如果一个处理器发生故障，则在更换整个处理单元之前，至少暂时在处理单元的其他两个处理器中继续操作。 此外，处理单元可以在时钟单元内具有多个时钟（A，B），具有切换装置，使得处理器通常从主时钟（A）接收时钟脉冲，但是从辅助时钟（B ）如果主时钟（A）失败。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 此外，多个高速缓冲存储器可以共同地连接到处理器，使得一个高速缓冲存储器的故障允许处理单元使用另一高速缓冲存储器继续操作。 可以通过直接比较来实现高速缓冲存储器的内容的一致性，并且还可以使用比较方法来使处理器的内部高速缓冲存储器中的数据与外部高速缓冲存储器中的数据不同。 协议的一致性还可以确保不同处理器单元的高速缓存中的数据总是正确的。

公开(公告)号：US5557753A

公开(公告)日：1996-09-17

申请号：US943001

申请日：1992-03-10

申请人： Masashi Suenaga ,  Nobuo Tomita ,  Hiroshi Watanabe ,  Masayuki Tanji

发明人： Masashi Suenaga ,  Nobuo Tomita ,  Hiroshi Watanabe ,  Masayuki Tanji

IPC分类号： G06F11/18 ,  G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A high-speed information processing in the information processing unit having a multiplexed bus is provided. A unit having a bus grant is stored in the next lowest priority unit memory circuits, and in the next bus arbitration cycle, bus arbitration is carried out by setting the lowest priority to the unit stored in the next lowest priority unit memory circuits. When a fault occurs in one of a plurality of buses and then the faulty bus recovered a normal operation status, the bus status supervising circuits output has fault recovery detecting signals and match the memory contents of the next lowest priority unit memory circuits together. With the above arrangement, an average bus waiting time can be minimized and the bus waiting time can be limited.

摘要翻译： 提供具有复用总线的信息处理单元中的高速信息处理。 具有总线许可的单元被存储在下一个最低优先级单元存储电路中，并且在下一个总线仲裁周期中，通过将最低优先级设置为存储在下一个最低优先级单元存储电路中的单元来执行总线仲裁。 当在多个总线之一发生故障，然后故障总线恢复正常操作状态时，总线状态监控电路输出具有故障恢复检测信号，并将下一个最低优先级单元存储器电路的存储器内容匹配在一起。 通过上述配置，能够使总线等待时间平均化，能够限制总线等待时间。

公开(公告)号：US5345566A

公开(公告)日：1994-09-06

申请号：US825063

申请日：1992-01-24

申请人： Masayuki Tanji ,  Yoshihiro Miyazaki ,  Hiroaki Fukumaru ,  Syoji Yamaguchi ,  Koji Masui ,  Hisao Ogawa

发明人： Masayuki Tanji ,  Yoshihiro Miyazaki ,  Hiroaki Fukumaru ,  Syoji Yamaguchi ,  Koji Masui ,  Hisao Ogawa

IPC分类号： G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F13/00 ,  G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4022 ,  G06F13/364

摘要： A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.

摘要翻译： 一种用于控制双总线系统的方法和装置，即使双总线系统的总线之一发生故障，也能够实现高速和连续的操作。 该方法和装置具有双总线系统，连接到双总线系统的两个总线的多个电子电路和用于向多个电子电路之一提供总线使用允许信号的总线控制器，所选择的一个电子电路 根据从多个电子电路发出的请求数据传送的总线占用请求信号。 如果双总线系统的两个总线的总线占用请求信号来自一个选定的电子电路，并且仲裁器的输出一致，那么总线使用允许信号被提供给一个所选择的电子电路，以允许占用两条总线的 双总线系统。 在两条总线完成数据传输时，确定双总线系统的数据传输完成。 在出现故障时可以立即确保持续运转，能够实现计算机系统的高速运转。