公开(公告)号：US20070263456A1

公开(公告)日：2007-11-15

申请号：US11748541

申请日：2007-05-15

Applicant: Bin Wang ,  Chih-Hsin Wang ,  William Colleran

Inventor： Bin Wang ,  Chih-Hsin Wang ,  William Colleran

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract translation: NVM阵列包括包括浮动栅极和四晶体管存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

公开(公告)号：US08264039B2

公开(公告)日：2012-09-11

申请号：US10952708

申请日：2004-09-28

Applicant: Bin Wang ,  William T. Colleran ,  Chih-Hsin Wang

Inventor： Bin Wang ,  William T. Colleran ,  Chih-Hsin Wang

IPC: H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/7835

Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.

Abstract translation: 高压LDMOSFET包括其中形成栅极阱的半导体衬底。 源极阱和漏极阱形成在栅极阱的任一侧上，并且在其内部包括未达到全部深度的绝缘区域。 绝缘层设置在衬底上，覆盖栅极阱以及源极阱和漏极阱的一部分。 导电栅极设置在绝缘层上。 在源阱和排水井附近形成偏置井。 在衬底中形成深阱，使得其在偏压井和浇口井下连通，同时在源井和排水井下方延伸，以避免它们。 偏置井顶部的偏置接触偏压深井，因此井也很好。

公开(公告)号：US20060001050A1

公开(公告)日：2006-01-05

申请号：US11138888

申请日：2005-05-26

Applicant: Bin Wang ,  Chih-Hsin Wang

Inventor： Bin Wang ,  Chih-Hsin Wang

IPC: H01L29/745 ,  H01L21/335

CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底，衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中，包括第二类型的掺杂植入物，并且适于接收源极接触。 这样，第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方，并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。

公开(公告)号：US20050258461A1

公开(公告)日：2005-11-24

申请号：US10952708

申请日：2004-09-28

Applicant: Bin Wang ,  William Colleran ,  Chih-Hsin Wang

Inventor： Bin Wang ,  William Colleran ,  Chih-Hsin Wang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/7835

Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.

Abstract translation: 高压LDMOSFET包括其中形成栅极阱的半导体衬底。 源极阱和漏极阱形成在栅极阱的任一侧上，并且在其内部包括未达到全部深度的绝缘区域。 绝缘层设置在衬底上，覆盖栅极阱以及源极阱和漏极阱的一部分。 导电栅极设置在绝缘层上。 在源阱和排水井附近形成偏置井。 在衬底中形成深阱，使得其在偏压井和浇口井下连通，同时在源井和排水井下方延伸，以避免它们。 偏置井顶部的偏置接触偏压深井，因此井也很好。

公开(公告)号：US07375398B2

公开(公告)日：2008-05-20

申请号：US11138888

申请日：2005-05-26

Applicant: Bin Wang ,  Chih-Hsin Wang

Inventor： Bin Wang ,  Chih-Hsin Wang

IPC: H01L23/62

CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底，衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中，包括第二类型的掺杂植入物，并且适于接收源极接触。 这样，第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方，并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。

公开(公告)号：US20060209598A1

公开(公告)日：2006-09-21

申请号：US11084214

申请日：2005-03-17

Applicant: Bin Wang ,  Chih-Hsin Wang ,  William Colleran

Inventor： Bin Wang ,  Chih-Hsin Wang ,  William Colleran

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract translation: NVM阵列包括包括浮动栅极，双晶体管，逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

公开(公告)号：US07257033B2

公开(公告)日：2007-08-14

申请号：US11084214

申请日：2005-03-17

Applicant: Bin Wang ,  Chih-Hsin Wang ,  William T. Colleran

Inventor： Bin Wang ,  Chih-Hsin Wang ,  William T. Colleran

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract translation: NVM阵列包括包括浮动栅极，双晶体管，逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

公开(公告)号：US08270234B1

公开(公告)日：2012-09-18

申请号：US13113303

申请日：2011-05-23

Applicant: Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

Inventor： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  H03K3/356052 ,  H03K3/356113

Abstract: A level shifter including a level shifter module configured to i) receive an input signal, wherein the input signal varies between a first level and a second level, ii) receive a first voltage supply signal and a second voltage supply signal, and iii) generate a latch control signal based on the input signal and one of the first voltage supply signal and the second voltage supply signal. The level shifter further includes a latch module configured to i) receive the latch control signal, ii) receive the second voltage supply signal and a third voltage supply signal, and iii) generate an output signal based on the latch control signal and one of the second voltage supply signal and the third voltage supply signal.

Abstract translation: 一种电平移位器，包括电平移位器模块，其配置为i）接收输入信号，其中所述输入信号在第一电平和第二电平之间变化，ii）接收第一电压供应信号和第二电压供应信号，以及iii）产生 基于输入信号和第一电压供给信号和第二电压供给信号中的一个的锁存器控制信号。 电平移位器还包括锁存模块，其被配置为i）接收锁存控制信号，ii）接收第二电压供应信号和第三电压供应信号，以及iii）基于锁存控制信号产生输出信号，并且 第二电压供给信号和第三电压供给信号。

公开(公告)号：US08120088B1

公开(公告)日：2012-02-21

申请号：US12105988

申请日：2008-04-18

Applicant: Min She ,  Chih-Hsin Wang

Inventor： Min She ,  Chih-Hsin Wang

IPC: H01L29/76

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5×1019 atoms/cm3.

Abstract translation: 存储单元和阵列降低了位线电阻。 元件导体设置在位线的顶部以减小位线的电阻，同时保持浅位线结，使得通过20位或更浅的位线结实现200欧姆/平方或更小的薄层电阻，同时 结中的掺杂水平低于约5×1019原子/ cm3。

公开(公告)号：US20070253257A1

公开(公告)日：2007-11-01

申请号：US11380418

申请日：2006-04-26

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: G11C16/04

CPC classification number: H01L29/7885 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324

Abstract: Nonvolatile memory cells and array are provided. The memory cell comprises a body, a source, a drain, and a charge storage region. The body comprises an n-type conductivity and is formed in a well of the n-type conductivity. The source and the drain have p-type conductivity and are formed in the well with a channel of the body defined therebetween. The charge storage region is disposed over and insulated from the channel by a channel insulator. Each cell further comprises a bias setting having a source voltage applied to the source, a well voltage applied to the well, and a drain voltage applied to the drain. A bias configuration for an erase operation of the memory cell is further provided, wherein the source voltage is sufficiently more negative with respect to the well voltage and is sufficiently more positive with respect to the drain voltage to inject hot holes onto the charge storage region. The cells can be arranged in row and column to form memory arrays and memory device.

Abstract translation: 提供了非易失性存储单元和阵列。 存储单元包括主体，源极，漏极和电荷存储区域。 该主体包括n型导电性并形成在n型导电性的阱中。 源极和漏极具有p型导电性，并且在阱中形成有在其间限定的主体的沟道。 电荷存储区域通过沟道绝缘体设置在通道上并与通道绝缘。 每个单元还包括具有施加到源极的源极电压，施加到阱的阱电压和施加到漏极的漏极电压的偏置设置。 还提供了用于存储单元的擦除操作的偏置配置，其中源极电压相对于阱电压足够多地为负，并且相对于漏极电压而言足够地为正向，以将热空穴注入电荷存储区域。 单元格可以以行和列排列以形成存储器阵列和存储器件。