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公开(公告)号:US08143162B2
公开(公告)日:2012-03-27
申请号:US12500796
申请日:2009-07-10
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
CPC分类号: H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
摘要翻译: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底,半导体衬底上的低k电介质层,低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。
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公开(公告)号:US07629273B2
公开(公告)日:2009-12-08
申请号:US11523674
申请日:2006-09-19
申请人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L21/31 , H01L21/469
CPC分类号: H01L21/3105 , H01L21/823807 , H01L29/7843
摘要: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.
摘要翻译: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底,在第一器件区域中形成金属氧化物半导体(MOS)器件,在MOS器件上形成应力层,并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线(UV)固化,激光固化,电子束固化及其组合组成的组。
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公开(公告)号:US20090275195A1
公开(公告)日:2009-11-05
申请号:US12500796
申请日:2009-07-10
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
IPC分类号: H01L21/768
CPC分类号: H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
摘要翻译: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底,半导体衬底上的低k电介质层,低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。
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公开(公告)号:US20080085607A1
公开(公告)日:2008-04-10
申请号:US11523674
申请日:2006-09-19
申请人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L21/31
CPC分类号: H01L21/3105 , H01L21/823807 , H01L29/7843
摘要: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.
摘要翻译: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底,在第一器件区域中形成金属氧化物半导体(MOS)器件,在MOS器件上形成应力层,并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线(UV)固化,激光固化,电子束固化及其组合组成的组。
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公开(公告)号:US09385034B2
公开(公告)日:2016-07-05
申请号:US11786367
申请日:2007-04-11
申请人: Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L23/48 , H01L23/52 , H01L29/40 , H01L21/768
CPC分类号: H01L21/76849 , H01L21/76856 , H01L21/76883
摘要: An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.
摘要翻译: 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的导电布线; 以及导电布线上的金属碳化物盖层。
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公开(公告)号:US20080251928A1
公开(公告)日:2008-10-16
申请号:US11786367
申请日:2007-04-11
申请人: Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L23/532 , H01L21/768
CPC分类号: H01L21/76849 , H01L21/76856 , H01L21/76883
摘要: An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.
摘要翻译: 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的导电布线; 以及导电布线上的金属碳化物盖层。
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公开(公告)号:US20100090343A1
公开(公告)日:2010-04-15
申请号:US12638022
申请日:2009-12-15
申请人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
发明人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号: H01L23/48
CPC分类号: H01L23/53238 , H01L21/28556 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L21/76889 , H01L23/528 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
摘要翻译: 提供了形成在第一介电层中的铜互连结构的盖层。 在一个实施例中,盖层可以通过原位沉积工艺形成,其中引入包含锗,砷,钨或镓的工艺气体,从而形成铜 - 金属帽层。 在另一个实施例中,提供铜 - 金属硅化物帽。 在该实施方案中,在引入工艺气体之前,期间或之后引入硅烷,该工艺气体包括锗,砷,钨或镓。 此后,可以形成可选的蚀刻停止层,并且可以在蚀刻停止层或第一介电层上方形成第二介电层。
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公开(公告)号:US20080233745A1
公开(公告)日:2008-09-25
申请号:US11738982
申请日:2007-04-23
申请人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
发明人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号: H01L21/441
CPC分类号: H01L23/53238 , H01L21/28556 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L21/76889 , H01L23/528 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
摘要翻译: 提供了形成在第一介电层中的铜互连结构的盖层。 在一个实施例中,盖层可以通过原位沉积工艺形成,其中引入包含锗,砷,钨或镓的工艺气体,从而形成铜 - 金属帽层。 在另一个实施例中,提供铜 - 金属硅化物帽。 在该实施方案中,在引入工艺气体之前,期间或之后引入硅烷,该工艺气体包括锗,砷,钨或镓。 此后,可以形成可选的蚀刻停止层,并且可以在蚀刻停止层或第一介电层上方形成第二介电层。
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公开(公告)号:US20120049371A1
公开(公告)日:2012-03-01
申请号:US13290811
申请日:2011-11-07
申请人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
发明人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号: H01L23/532
CPC分类号: H01L23/53238 , H01L21/28556 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L21/76889 , H01L23/528 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
摘要翻译: 提供了形成在第一介电层中的铜互连结构的盖层。 在一个实施例中,导电层位于电介质层内,并且导电层的顶表面具有凹陷,凸面或平面。 合金层覆盖在导电层上,并且是具有来自导电层的第一材料和锗,砷,钨或镓的第二材料的硅化物合金。
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公开(公告)号:US08330275B2
公开(公告)日:2012-12-11
申请号:US13290811
申请日:2011-11-07
申请人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
发明人: Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号: H01L23/52
CPC分类号: H01L23/53238 , H01L21/28556 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L21/76889 , H01L23/528 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
摘要翻译: 提供了形成在第一介电层中的铜互连结构的盖层。 在一个实施例中,导电层位于电介质层内,并且导电层的顶表面具有凹陷,凸面或平面。 合金层覆盖在导电层上,并且是具有来自导电层的第一材料和锗,砷,钨或镓的第二材料的硅化物合金。
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