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公开(公告)号:US07629273B2
公开(公告)日:2009-12-08
申请号:US11523674
申请日:2006-09-19
申请人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L21/31 , H01L21/469
CPC分类号: H01L21/3105 , H01L21/823807 , H01L29/7843
摘要: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.
摘要翻译: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底,在第一器件区域中形成金属氧化物半导体(MOS)器件,在MOS器件上形成应力层,并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线(UV)固化,激光固化,电子束固化及其组合组成的组。
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公开(公告)号:US20090275195A1
公开(公告)日:2009-11-05
申请号:US12500796
申请日:2009-07-10
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
IPC分类号: H01L21/768
CPC分类号: H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
摘要翻译: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底,半导体衬底上的低k电介质层,低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。
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公开(公告)号:US20080085607A1
公开(公告)日:2008-04-10
申请号:US11523674
申请日:2006-09-19
申请人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L21/31
CPC分类号: H01L21/3105 , H01L21/823807 , H01L29/7843
摘要: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.
摘要翻译: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底,在第一器件区域中形成金属氧化物半导体(MOS)器件,在MOS器件上形成应力层,并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线(UV)固化,激光固化,电子束固化及其组合组成的组。
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公开(公告)号:US08143162B2
公开(公告)日:2012-03-27
申请号:US12500796
申请日:2009-07-10
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
CPC分类号: H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
摘要翻译: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底,半导体衬底上的低k电介质层,低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。
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公开(公告)号:US08324731B2
公开(公告)日:2012-12-04
申请号:US12591532
申请日:2009-11-23
申请人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
发明人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
IPC分类号: H01L21/31
CPC分类号: B29C43/222 , A44B17/0029 , A44B17/0058 , B29C43/28 , B29C2793/009 , B29L2031/7282 , B29L2031/729 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2224/45099
摘要: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
摘要翻译: 提供了至少具有用于半导体器件的接合焊盘的集成电路器件及其制造方法。 接合焊盘具有具有多个开口的第一钝化层。 覆盖在开口和第一钝化层的部分上的导电层,其具有覆盖第一钝化层的第一部分和覆盖开口的第二部分。 第二钝化层覆盖在第一钝化层上并覆盖导电层的边缘。
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公开(公告)号:US20100065969A1
公开(公告)日:2010-03-18
申请号:US12591532
申请日:2009-11-23
申请人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
发明人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
IPC分类号: H01L23/532 , H01L23/48
CPC分类号: B29C43/222 , A44B17/0029 , A44B17/0058 , B29C43/28 , B29C2793/009 , B29L2031/7282 , B29L2031/729 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2224/45099
摘要: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
摘要翻译: 提供了至少具有用于半导体器件的接合焊盘的集成电路器件及其制造方法。 接合焊盘具有具有多个开口的第一钝化层。 覆盖在开口和第一钝化层的部分上的导电层,其具有覆盖第一钝化层的第一部分和覆盖开口的第二部分。 第二钝化层覆盖在第一钝化层上并覆盖导电层的边缘。
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公开(公告)号:US07646097B2
公开(公告)日:2010-01-12
申请号:US11246088
申请日:2005-10-11
申请人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
发明人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
IPC分类号: H01L23/48
CPC分类号: B29C43/222 , A44B17/0029 , A44B17/0058 , B29C43/28 , B29C2793/009 , B29L2031/7282 , B29L2031/729 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2224/45099
摘要: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
摘要翻译: 提供了用于半导体器件的接合焊盘及其制造方法。 接合焊盘具有具有多个开口的第一钝化层。 覆盖在开口和第一钝化层的部分上的导电层,其具有覆盖第一钝化层的第一部分和覆盖开口的第二部分。 第二钝化层覆盖在第一钝化层上并覆盖导电层的边缘。
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公开(公告)号:US20070080460A1
公开(公告)日:2007-04-12
申请号:US11246088
申请日:2005-10-11
申请人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
发明人: Chen-Hua Yu , Shwang-Ming Jeng , Yung-Cheng Lu , Huilin Chang , Ting-Yu Shen , Yichi Liao
IPC分类号: H01L23/52
CPC分类号: B29C43/222 , A44B17/0029 , A44B17/0058 , B29C43/28 , B29C2793/009 , B29L2031/7282 , B29L2031/729 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2224/45099
摘要: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
摘要翻译: 提供了用于半导体器件的接合焊盘及其制造方法。 接合焊盘具有具有多个开口的第一钝化层。 覆盖在开口和第一钝化层的部分上的导电层,其具有覆盖第一钝化层的第一部分和覆盖开口的第二部分。 第二钝化层覆盖在第一钝化层上并覆盖导电层的边缘。
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公开(公告)号:US20060226549A1
公开(公告)日:2006-10-12
申请号:US11104266
申请日:2005-04-12
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号: H01L23/52 , H01L21/4763
CPC分类号: H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device and a fabrication method thereof. The semiconductor device has a substrate with a first conductive area, a dielectric layer formed of a low dielectric constant material disposed on the substrate, and a dielectric anti-reflective coating (DARC) layer disposed on the dielectric layer. A contact hole is disposed in the DARC layer and the dielectric layer to the first conductive area and a contact plug is disposed in the contact hole and electrically connected to the first conductive area.
摘要翻译: 半导体器件及其制造方法。 该半导体器件具有一个具有第一导电区域的基片,一个由布置在该基片上的低介电常数材料形成的电介质层,以及设置在介电层上的介电抗反射涂层(DARC)层。 接触孔设置在DARC层中,电介质层设置到第一导电区域,接触插头设置在接触孔中并电连接到第一导电区域。
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公开(公告)号:US08987085B2
公开(公告)日:2015-03-24
申请号:US11524000
申请日:2006-09-20
申请人: Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
发明人: Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号: H01L21/768 , H01L21/02 , H01L21/3105
CPC分类号: H01L21/76849 , H01L21/02074 , H01L21/3105 , H01L21/76826
摘要: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.
摘要翻译: 形成集成电路的方法包括提供半导体衬底,在半导体衬底上形成金属化层,其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层,对低k电介质层进行处理以形成亲水性顶表面,以及在溶液中的金属特征上镀覆盖层。
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