利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

153 条记录 (耗时 0.022 秒)

    Method of patterning damascene structure in integrated circuit design
    1.
    发明授权
    Method of patterning damascene structure in integrated circuit design 失效

    公开(公告)号：US06949459B2

    公开(公告)日：2005-09-27

    申请号：US10704022

    申请日：2003-11-07

    申请人： Wai-Kin Li ,  Chih-Chao Yang ,  Yi-hsiung Lin

    发明人： Wai-Kin Li ,  Chih-Chao Yang ,  Yi-hsiung Lin

    IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76831

    摘要： Disclosed is a method that deposits an aqueous material having a pH between approximately 10 and 11 in a first opening and on an oxide hard mask, deposits an organic material on the aqueous material, and patterns a photoresist over the organic material. The invention then etches the organic material and the aqueous material through the photoresist to form a second opening above the first opening and forms a polymer along sidewalls of the second opening. The invention can then perform a wet cleaning process using an alkali solution having a pH between approximately 10 and 11 to remove the aqueous material from the first opening. By utilizing an alkali aqueous (water-based) material having a pH of approximately 10-11, the invention can use a fairly low pH wet etch (pH of approximately 10-11) to completely remove the aqueous solution from the via, thereby eliminating the conventional problem of having residual organic material left within the via.

    METHOD OF FORMATION OF A DAMASCENE STRUCTURE
    2.
    发明申请
    METHOD OF FORMATION OF A DAMASCENE STRUCTURE 审中-公开
    形成大分子结构的方法

    公开(公告)号：US20080020327A1

    公开(公告)日：2008-01-24

    申请号：US11458499

    申请日：2006-07-19

    申请人： Chih-Chao Yang ,  Wai-Kin Li ,  Yi-Hsiung Lin

    发明人： Chih-Chao Yang ,  Wai-Kin Li ,  Yi-Hsiung Lin

    IPC分类号： G03F7/26

    CPC分类号： H01L21/76808

    摘要： A method in which during the formation of damascene features in a semiconductor structure, a planarization material is added to vias formed in the dielectric to protect the vias during subsequent lithographic processing. The planarization material preferred is a developable photosensitive material which can be exposed and developed to define the damascene features rather than etching as is conventional.

    摘要翻译： 一种在半导体结构中形成镶嵌特征的方法中，将平坦化材料添加到在电介质中形成的通孔中，以在随后的光刻处理期间保护通孔。 优选的平坦化材料是可显影的感光材料，其可以暴露和显影以限定镶嵌特征，而不是如常规的蚀刻。

    Semiconductor structure and method of manufacturing same
    3.
    发明授权
    Semiconductor structure and method of manufacturing same 有权
    半导体结构及其制造方法

    公开(公告)号：US07960036B2

    公开(公告)日：2011-06-14

    申请号：US11831005

    申请日：2007-07-31

    申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

    发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

    IPC分类号： B32B9/00 ,  B32B19/00 ,  B32B15/04

    CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

    摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

    摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
    4.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME 有权
    半导体结构及其制造方法

    公开(公告)号：US20090035588A1

    公开(公告)日：2009-02-05

    申请号：US11831005

    申请日：2007-07-31

    申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

    发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

    IPC分类号： B32B15/04 ,  H01L21/44

    CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

    摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

    摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

    Semiconductor structure and method of manufacturing same
    5.
    发明授权
    Semiconductor structure and method of manufacturing same 有权
    半导体结构及其制造方法

    公开(公告)号：US08298912B2

    公开(公告)日：2012-10-30

    申请号：US13080326

    申请日：2011-04-05

    申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

    发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

    IPC分类号： H01L21/76

    CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

    摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

    摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

    STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES
    6.
    发明申请
    STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES 失效
    减少半导体器件中的电化学破碎和挤出效应的结构和方法

    公开(公告)号：US20080303164A1

    公开(公告)日：2008-12-11

    申请号：US11758206

    申请日：2007-06-05

    申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L23/52 ,  H01L21/44

    CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

    摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在第二介电层中的空隙，停止在盖层上，其中，空隙以如下方式定位，以便隔离由于第一金属线的电迁移效应引起的结构损坏，包括一种或多种金属挤压的效果 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

    STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES
    9.
    发明申请
    STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES 失效
    减少半导体器件中的电化学破碎和挤出效应的结构和方法

    公开(公告)号：US20120264295A1

    公开(公告)日：2012-10-18

    申请号：US13530999

    申请日：2012-06-22

    申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L21/44

    CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

    摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

    Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices
    10.
    发明授权
    Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices 失效
    减少半导体器件中电迁移破裂和挤出效应的结构和方法

    公开(公告)号：US08716101B2

    公开(公告)日：2014-05-06

    申请号：US13530999

    申请日：2012-06-22

    申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L21/76

    CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

    摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。