公开(公告)号：US09152497B2

公开(公告)日：2015-10-06

申请号：US13974997

申请日：2013-08-23

申请人： Dana Lee ,  Abhijeet Manohar

发明人： Dana Lee ,  Abhijeet Manohar

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C16/34 ,  G11C29/50 ,  G11C29/04

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C16/3431 ,  G11C29/00 ,  G11C29/50004 ,  G11C29/50008 ,  G11C2029/0411 ,  G11C2029/5002

摘要： A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.

摘要翻译： 存储模块可以包括NAND型闪存阵列和一个或多个控制器，其被配置为增加施加到存储器阵列中的栅极的栅极偏置电压电平，以克服可能的栅极短路并恢复被识别为不可校正的数据。 增加的栅极偏置电压可以施加到单个晶体管的栅极或存储器阵列中的不同类型的晶体管，包括漏极选择晶体管，源极选择晶体管或浮动栅极晶体管。

公开(公告)号：US20150058698A1

公开(公告)日：2015-02-26

申请号：US13974997

申请日：2013-08-23

申请人： Dana Lee ,  Abhijeet Manohar

发明人： Dana Lee ,  Abhijeet Manohar

IPC分类号： G06F11/10 ,  G11C29/00

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C16/3431 ,  G11C29/00 ,  G11C29/50004 ,  G11C29/50008 ,  G11C2029/0411 ,  G11C2029/5002

摘要： A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.

摘要翻译： 存储模块可以包括NAND型闪存阵列和一个或多个控制器，其被配置为增加施加到存储器阵列中的栅极的栅极偏置电压电平，以克服可能的栅极短路并恢复被识别为不可校正的数据。 增加的栅极偏置电压可以施加到单个晶体管的栅极或存储器阵列中的不同类型的晶体管，包括漏极选择晶体管，源极选择晶体管或浮动栅极晶体管。

公开(公告)号：US08953398B2

公开(公告)日：2015-02-10

申请号：US13527199

申请日：2012-06-19

申请人： Dana Lee ,  Jianmin Huang ,  Mrinal Kochar ,  Ashish Ghai

发明人： Dana Lee ,  Jianmin Huang ,  Mrinal Kochar ,  Ashish Ghai

IPC分类号： G11C7/00

CPC分类号： G11C16/349 ,  G11C29/56008 ,  G11C29/82 ,  G11C2029/4402

摘要： A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.

摘要翻译： 可以使用用于分级块的系统来改善存储器使用。 诸如闪存卡之类的存储器块可以在可以标识每个块的“良好”级别或“坏”级别的滑动标度上分级，而不是二进制好或坏标识。 该分级系统可以利用至少三个等级的等级，其可以通过基于每个块的各个等级更好地利用每个块来提高效率。 块调平分级系统可用于优化最小化产量损失的竞争需求，同时最小化测试缺陷逃逸。

公开(公告)号：US20130128666A1

公开(公告)日：2013-05-23

申请号：US13435476

申请日：2012-03-30

申请人： Chris Avila ,  Jianmin Huang ,  Dana Lee

发明人： Chris Avila ,  Jianmin Huang ,  Dana Lee

IPC分类号： G11C16/26

CPC分类号： G06F11/1048 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/5634

摘要： The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected.

摘要翻译： 关于是否刷新或退出内存块的决定是基于正在使用的一组动态读取值。 在使用动态读取值表的存储器系统中，该表被配置为包括如何处理读取错误（退出，刷新）以及不同动态读取情况的读取参数。 在细化中，读取案例编号可用于为选择刷新或退出的块确定优先级。 在读取擦除更精确的情况下，可以应用多个动态读取情况。 此外，可以智能地选择应用哪些情况。

公开(公告)号：US20120300550A1

公开(公告)日：2012-11-29

申请号：US13113786

申请日：2011-05-23

申请人： Gerrit Jan Hemink ,  Shih-Chung Lee ,  Anubhav Khandelwal ,  Henry Chin ,  Guirong Liang ,  Dana Lee

发明人： Gerrit Jan Hemink ,  Shih-Chung Lee ,  Anubhav Khandelwal ,  Henry Chin ,  Guirong Liang ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/10

摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.

摘要翻译： 在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。 在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。 增加可以是渐进的，以斜坡的形式，或逐步的。 可以维持第一通道区域的升压水平。 施加到一个或多个未选择字线的电压的增加也随着温度而变化。 在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

公开(公告)号：US08184479B2

公开(公告)日：2012-05-22

申请号：US13221147

申请日：2011-08-30

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

公开(公告)号：US08164135B2

公开(公告)日：2012-04-24

申请号：US12773811

申请日：2010-05-04

申请人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

发明人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

IPC分类号： H01L29/788

CPC分类号： G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

摘要翻译： 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

公开(公告)号：US07800956B2

公开(公告)日：2010-09-21

申请号：US12163073

申请日：2008-06-27

申请人： Dana Lee ,  Deepanshu Dutta ,  Yingda Dong

发明人： Dana Lee ,  Deepanshu Dutta ,  Yingda Dong

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.

摘要翻译： 在多遍编程过程中，非易失性存储器中的编程时间会减少。 在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。 一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。 此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。 在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。 与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

公开(公告)号：US07577034B2

公开(公告)日：2009-08-18

申请号：US11861909

申请日：2007-09-26

申请人： Dana Lee ,  Jun Wan

发明人： Dana Lee ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C29/00

摘要： A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.

摘要翻译： 采取校正动作来调整应用于存储器件中的选定字线的编程电压中的非线性。 非线性导致不均匀的程序电压步长，这可能导致过度编程或缓慢编程。 提供程序电压的数模转换器（DAC）可以具有非线性输出，例如当某些代码字被输入到DAC时。 可以预先测试存储器件以确定非线性发生的位置，并且配置为在输入相应的代码字时采取校正动作。 例如，当输入翻转代码字时，DAC可以具有非线性输出，例如，当连续代码字中的最低有效位的串从1变为0时。 校正动作可以包括重复先前的编程脉冲或调整编程脉冲的持续时间。

公开(公告)号：US20090161433A1

公开(公告)日：2009-06-25

申请号：US11961871

申请日：2007-12-20

申请人： Dana Lee ,  Nima Mokhlesi ,  Deepak Chandra Sekar

发明人： Dana Lee ,  Nima Mokhlesi ,  Deepak Chandra Sekar

IPC分类号： G11C16/10 ,  G11C16/26

CPC分类号： G11C16/30

摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.

摘要翻译： 提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。 误差是由电流流动时芯片地线源极电阻的电压降引起的。 为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元 的结构块现在已经跑到地面上了。 变化包括可在聚集节点和地之间连接的非线性电阻元件。