公开(公告)号：US08472266B2

公开(公告)日：2013-06-25

申请号：US13077778

申请日：2011-03-31

申请人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

发明人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.

摘要翻译： 公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。 技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。 例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。 在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。 将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

公开(公告)号：US20120250414A1

公开(公告)日：2012-10-04

申请号：US13077778

申请日：2011-03-31

申请人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

发明人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.

摘要翻译： 公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。 技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。 例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。 在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。 将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

公开(公告)号：US20090080263A1

公开(公告)日：2009-03-26

申请号：US11861909

申请日：2007-09-26

申请人： Dana Lee ,  Jun Wan

发明人： Dana Lee ,  Jun Wan

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C29/00

摘要： A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.

摘要翻译： 采取校正动作来调整应用于存储器件中的选定字线的编程电压中的非线性。 非线性导致不均匀的程序电压步长，这可能导致过度编程或缓慢编程。 提供程序电压的数模转换器（DAC）可以具有非线性输出，例如当某些代码字被输入到DAC时。 可以预先测试存储器件以确定非线性发生的位置，并且配置为在输入相应的代码字时采取校正动作。 例如，当输入翻转代码字时，DAC可以具有非线性输出，例如，当连续代码字中的最低有效位的串从1变为0时。 校正动作可以包括重复先前的编程脉冲或调整编程脉冲的持续时间。

公开(公告)号：US07577034B2

公开(公告)日：2009-08-18

申请号：US11861909

申请日：2007-09-26

申请人： Dana Lee ,  Jun Wan

发明人： Dana Lee ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C29/00

摘要： A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.

摘要翻译： 采取校正动作来调整应用于存储器件中的选定字线的编程电压中的非线性。 非线性导致不均匀的程序电压步长，这可能导致过度编程或缓慢编程。 提供程序电压的数模转换器（DAC）可以具有非线性输出，例如当某些代码字被输入到DAC时。 可以预先测试存储器件以确定非线性发生的位置，并且配置为在输入相应的代码字时采取校正动作。 例如，当输入翻转代码字时，DAC可以具有非线性输出，例如，当连续代码字中的最低有效位的串从1变为0时。 校正动作可以包括重复先前的编程脉冲或调整编程脉冲的持续时间。

公开(公告)号：US09430322B2

公开(公告)日：2016-08-30

申请号：US13565650

申请日：2012-08-02

申请人： Jonathan Wolfman ,  Dana Lee ,  Jonathan Hsu

发明人： Jonathan Wolfman ,  Dana Lee ,  Jonathan Hsu

IPC分类号： G06F12/02 ,  G06F11/10 ,  H04L1/00 ,  G06F11/30 ,  G01R31/317 ,  G06F12/06 ,  G11C16/04 ,  G06F11/07 ,  G06F12/16 ,  G11C16/34 ,  G11C29/04

CPC分类号： G06F11/1048 ,  G01R31/3171 ,  G06F11/07 ,  G06F11/076 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/16 ,  G06F2212/7211 ,  G11C16/04 ,  G11C16/34 ,  G11C16/349 ,  G11C2029/0409 ,  H04L1/0061

摘要： A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.

摘要翻译： 可以使用用于改善基于固有耐力的块的管理和使用的系统来改善诸如存储卡的闪存的存储器使用。 整体卡耐力可以通过在最差块的最低耐力目标下具有较高内在耐力的循环块来延长。 这可以通过内部管理具有不同内在耐力值的块来实现，或者通过外部对不同的内在耐力值进行分区，以实现不同的使用。

公开(公告)号：US09152497B2

公开(公告)日：2015-10-06

申请号：US13974997

申请日：2013-08-23

申请人： Dana Lee ,  Abhijeet Manohar

发明人： Dana Lee ,  Abhijeet Manohar

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C16/34 ,  G11C29/50 ,  G11C29/04

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C16/3431 ,  G11C29/00 ,  G11C29/50004 ,  G11C29/50008 ,  G11C2029/0411 ,  G11C2029/5002

摘要： A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.

摘要翻译： 存储模块可以包括NAND型闪存阵列和一个或多个控制器，其被配置为增加施加到存储器阵列中的栅极的栅极偏置电压电平，以克服可能的栅极短路并恢复被识别为不可校正的数据。 增加的栅极偏置电压可以施加到单个晶体管的栅极或存储器阵列中的不同类型的晶体管，包括漏极选择晶体管，源极选择晶体管或浮动栅极晶体管。

公开(公告)号：US09053808B2

公开(公告)日：2015-06-09

申请号：US13529522

申请日：2012-06-21

申请人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

发明人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

IPC分类号： G06F11/00 ,  G11C16/34 ,  G11B20/18

CPC分类号： G11C16/3418 ,  G11B20/18 ,  G11B20/1883 ,  G11C16/3427 ,  G11C16/3431

摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.

摘要翻译： 已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。 该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。 控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。 然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。 块刷新过程可以包括在后台操作期间将数据从块复制到新块中。

公开(公告)号：US08854900B2

公开(公告)日：2014-10-07

申请号：US13559377

申请日：2012-07-26

申请人： Dana Lee ,  Yi-Chieh Chen ,  Farookh Moogat

发明人： Dana Lee ,  Yi-Chieh Chen ,  Farookh Moogat

IPC分类号： G11C7/00

CPC分类号： G11C5/14 ,  G11C16/30

摘要： A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.

摘要翻译： 具有多个存储器骰子的非易失性存储器管理同时操作，以便不超过系统功率容量。 负载信号总线以与系统功率容量成比例的强度被拉高。 每个模具具有一个驱动器，用于将总线的数量下降一定量，与模具状态机所估计的功率需求量相对应。 因此，总线提供负载信号，用作系统功率容量和单个骰子的累积负载之间的仲裁。 因此，当不超过系统功率容量时，负载信号处于高电平状态; 否则处于低状态。 当模具希望执行操作并请求一定量的电力时，它相应地驱动总线，并且其状态机根据负载信号进行操作。

公开(公告)号：US08780642B2

公开(公告)日：2014-07-15

申请号：US12872351

申请日：2010-08-31

申请人： Yuniarto Widjaja ,  John W. Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

发明人： Yuniarto Widjaja ,  John W. Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C2216/18 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。 在第一区域和第二区域之间限定连续的第一通道区域。 多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。 设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。 每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

公开(公告)号：US08750042B2

公开(公告)日：2014-06-10

申请号：US13332780

申请日：2011-12-21

申请人： Eran Sharon ,  Yan Li ,  Dana Lee ,  Idan Alrod

发明人： Eran Sharon ,  Yan Li ,  Dana Lee ,  Idan Alrod

IPC分类号： G11C29/04

CPC分类号： G11C29/04 ,  G11C11/5642 ,  G11C16/3459 ,  G11C29/50004 ,  G11C2211/5641

摘要： Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

摘要翻译： 介绍了写入后读取技术。 在示例性实施例中，使用多个字线的组合同时感测以便识别这些字线中的一个或多个中的问题。 也就是说，感测电压同时施加到多个存储单元的控制栅极，其结果电导在同一位线上被测量。 组合的感测结果用于测量多个字线的单元电压分布（CVD）的某些统计量并将其与预期值进行比较。 在测量的统计量与预期不同的情况下，这可以指示感测字线中的一个或多个可能表现出故障，并且可以执行对该组字线的更彻底的检查。