公开(公告)号：US20170192112A1

公开(公告)日：2017-07-06

申请号：US14986001

申请日：2015-12-31

Applicant: General Electric Company

Inventor： Peter Micah Sandvik ,  Stanislav Ivanovich Soloviev ,  Sergei Ivanovich Dolinsky ,  James Jay McMahon ,  Sabarni Palit

IPC: G01T1/24 ,  H01L31/115

CPC classification number: G01T1/248 ,  G01T1/2018 ,  G01T1/208 ,  G01T1/249 ,  H01L27/14663 ,  H01L31/02027 ,  H01L31/107 ,  H01L31/115

Abstract: A solid state photomultiplier includes at least one microcell configured to generate an initial analog signal when exposed to optical photons. The solid state photomultiplier further includes a quench circuit electrically coupled with the at least one microcell. The quench circuit includes at least one quench resistor configured to exhibit a substantially constant temperature coefficient of resistance over a selected temperature range.

公开(公告)号：US20150236151A1

公开(公告)日：2015-08-20

申请号：US14182765

申请日：2014-02-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： James Jay McMahon ,  Ljubisa Dragoljub Stevanovic ,  Stephen Daley Arthur ,  Thomas Bert Gorczyca ,  Richard Alfred Beaupre ,  Zachary Matthew Stum ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/16

CPC classification number: H01L29/7827 ,  H01L21/045 ,  H01L21/049 ,  H01L21/28247 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7816

Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.

Abstract translation: 介绍了半导体器件。 该器件包括具有碳化硅的半导体层，并具有第一表面和第二表面。 栅极绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅极绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的角部处的氧化物，因此栅极绝缘层在角部具有比层的中心处的厚度更大的厚度。 还提供了一种用于制造该装置的方法。

公开(公告)号：US08507986B2

公开(公告)日：2013-08-13

申请号：US13740758

申请日：2013-01-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Zachary Matthew Stum ,  Peter Almren Losee ,  James Jay McMahon

IPC: H01L29/76 ,  H01L21/332

CPC classification number: H01L27/088 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Abstract translation: 在一个实施例中，本发明包括一个包含单个MOSFET单元的MOSFET。 每个单元包括形成在井内的U形孔（P型）和两个平行的源（N型）。 在多个位置连接多个源极（掺杂N）源极。 两个梯级之间的区域包括一个主体（P型）。 这些特征形成在形成在N型衬底上的N型外延层上。 联系人跨越并接触许多源级和身体。 栅极氧化物和栅极接触覆盖第一阱的支腿和第二相邻阱的支路，响应于栅极电压而反转导电性。 MOSFET包括多个这些单元以获得期望的低通道电阻。 在制造过程的几个状态下使用自对准技术形成单元区域。

公开(公告)号：US10541338B2

公开(公告)日：2020-01-21

申请号：US16060549

申请日：2015-12-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  James Jay McMahon

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L29/167

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.

公开(公告)号：US10186509B2

公开(公告)日：2019-01-22

申请号：US15333868

申请日：2016-10-25

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/74 ,  H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L29/861 ,  H01L29/739

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

公开(公告)号：US10078143B2

公开(公告)日：2018-09-18

申请号：US14986001

申请日：2015-12-31

Applicant: General Electric Company

Inventor： Peter Micah Sandvik ,  Stanislav Ivanovich Soloviev ,  Sergei Ivanovich Dolinsky ,  James Jay McMahon ,  Sabarni Palit

IPC: G01T1/24 ,  H01L31/115

CPC classification number: G01T1/248 ,  G01T1/2018 ,  G01T1/208 ,  G01T1/249 ,  H01L27/14663 ,  H01L31/02027 ,  H01L31/107 ,  H01L31/115

Abstract: A solid state photomultiplier includes at least one microcell configured to generate an initial analog signal when exposed to optical photons. The solid state photomultiplier further includes a quench circuit electrically coupled with the at least one microcell. The quench circuit includes at least one quench resistor configured to exhibit a substantially constant temperature coefficient of resistance over a selected temperature range.

公开(公告)号：US09508841B2

公开(公告)日：2016-11-29

申请号：US13957115

申请日：2013-08-01

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/74 ,  H01L27/02 ,  H01L29/861 ,  H01L29/739

CPC classification number: H01L27/0617 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract translation: 提供功率晶体管组件和操作组件的方法。 所述功率晶体管组件包括在单个半导体衬底上的集成瞬态电压抑制，并且包括由宽带隙材料形成的晶体管，所述晶体管包括栅极端子，源极端子和漏极端子，所述晶体管还包括预定的最大允许量 栅极电压值以及由宽带隙材料形成的瞬态电压抑制（TVS）器件，所述TVS器件由所述晶体管形成为单个半导体器件，所述TVS器件电耦合到所述晶体管的至少一个栅极和 源极端子和漏极和源极端子，TVS器件包括被选择为大于预定的最大允许栅极电压值的击穿电压限制。

公开(公告)号：US20150034969A1

公开(公告)日：2015-02-05

申请号：US13957115

申请日：2013-08-01

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  James Jay McMahon ,  Ljubisa Dragoljub Stevanovic

IPC: H01L29/06 ,  H01L29/74 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L27/0617 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract translation: 提供功率晶体管组件和操作组件的方法。 所述功率晶体管组件包括在单个半导体衬底上的集成瞬态电压抑制，并且包括由宽带隙材料形成的晶体管，所述晶体管包括栅极端子，源极端子和漏极端子，所述晶体管还包括预定的最大允许量 栅极电压值以及由宽带隙材料形成的瞬态电压抑制（TVS）器件，所述TVS器件由所述晶体管形成为单个半导体器件，所述TVS器件电耦合到所述晶体管的至少一个栅极和 源极端子和漏极和源极端子，TVS器件包括被选择为大于预定的最大允许栅极电压值的击穿电压限制。

公开(公告)号：US20130126971A1

公开(公告)日：2013-05-23

申请号：US13740758

申请日：2013-01-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Zachary Matthew Stum ,  Peter Almren Losee ,  James Jay McMahon

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Abstract translation: 在一个实施例中，本发明包括一个包含单个MOSFET单元的MOSFET。 每个单元包括形成在井内的U形孔（P型）和两个平行的源（N型）。 在多个位置连接多个源极（掺杂N）源极。 两个梯级之间的区域包括一个主体（P型）。 这些特征形成在形成在N型衬底上的N型外延层上。 联系人跨越并接触许多源级和身体。 栅极氧化物和栅极接触覆盖第一阱的支腿和第二相邻阱的支路，响应于栅极电压而反转导电性。 MOSFET包括多个这些单元以获得期望的低通道电阻。 在制造过程的几个状态下使用自对准技术形成单元区域。