公开(公告)号：US09530662B2

公开(公告)日：2016-12-27

申请号：US14630676

申请日：2015-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Tamer Coskun ,  Moshe Preil

IPC: H01L21/027 ,  H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成多个形貌特征的基本上周期性的阵列，包括多个耐蚀刻的地形特征和至少一个划线斑点特征。 多个耐蚀刻的形貌特征限定了多个耐蚀刻限制孔，并且所述至少一个划线阱特征限定了具有与耐蚀刻限制孔不同的尺寸和/或形状的划线阱限制阱。 将嵌段共聚物沉积到限制孔中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻的地形特征指示耐蚀刻相，在每个耐蚀刻限制孔中形成耐蚀刻塞。

公开(公告)号：US09286434B2

公开(公告)日：2016-03-15

申请号：US14285739

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yi Zou ,  Wei-Long Wang ,  Azat Latypov ,  Tamer Coskun

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括在设计布局中标识DSA目标图案的位置。 DSA目标模式被分组成包括第一组的组，并且围绕第一组定义第一组边界。 所述方法还包括确定到所述第一组边界的相邻DSA目标图案是否是距离在所述第一组边界内的相邻DSA目标图案至少预定的最小保持距离。 该方法还包括确定第一组中的DSA目标模式是否兼容DSA。 使用第一组边界生成输出掩模图案。

公开(公告)号：US20150235839A1

公开(公告)日：2015-08-20

申请号：US14185491

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Tamer Coskun ,  Wei-Long Wang ,  Azat Latypov ,  Yi Zou

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0274 ,  H01L21/308

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖在半导体衬底上的辅助抗蚀刻填充形貌特征，并且使用光掩模来定义辅助耐蚀刻填充约束阱。 光掩模定义了辅助的可光刻印刷的掩模特征。 将嵌段共聚物沉积到辅助抗蚀填充密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 辅助抗蚀刻填充形貌特征指示耐腐蚀相以在辅助耐蚀刻填充密封阱中形成耐蚀刻塞。

公开(公告)号：US08975195B2

公开(公告)日：2015-03-10

申请号：US13757286

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Todd Lukanc ,  Christopher Heinz Clifford ,  Tamer Coskun

IPC: H01L21/31 ,  H01L21/3105 ,  H01L21/312 ,  G06F17/50 ,  H01L21/02

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  H01L21/02348 ,  Y10S438/942 ,  Y10S438/948

Abstract: A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.

Abstract translation: 制造光学光刻掩模的方法包括提供包括多个多边形的图案化布局设计，通过调整多个多边形中的一个或多个的多边形的宽度和长度来使用光学邻近校正（OPC）校正图案化布局设计，以产生 校正的图案布局设计，将校正的图案布局设计转换成掩模写入器兼容格式，以生成包括多个多边形的掩模写入器兼容的布局设计，并且利用大的多边形偏置多边形中的每个多边形 - 图案布局设计的尺度密度值，以产生偏置的掩模写入器兼容布局设计。

公开(公告)号：US20160247686A1

公开(公告)日：2016-08-25

申请号：US14630676

申请日：2015-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Tamer Coskun ,  Moshe Preil

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成多个形貌特征的基本上周期性的阵列，包括多个耐蚀刻的地形特征和至少一个划线斑点特征。 多个耐蚀刻的形貌特征限定了多个耐蚀刻限制孔，并且所述至少一个划线阱特征限定了具有与耐蚀刻限制孔不同的尺寸和/或形状的划线阱限制阱。 将嵌段共聚物沉积到限制孔中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻的地形特征指示耐蚀刻相，在每个耐蚀刻限制孔中形成耐蚀刻塞。

公开(公告)号：US09208275B2

公开(公告)日：2015-12-08

申请号：US14189465

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei-Long Wang ,  Azat Latypov ,  Yi Zou ,  Tamer Coskun

IPC: G06F17/50 ,  G03F1/00 ,  H01L21/027 ,  H01L21/311

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  H01L21/0271 ,  H01L21/0274 ,  H01L21/31133

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括输入DSA目标图案。 DSA目标图案被分组成包括第一组的组，并且组边界围绕第一组被定义为初始OPC掩模模式。 围绕第一组中的每个DSA目标图案生成圆目标以定义合并的圆目标边界。 使用合并的圆目标边界来调整和/或迭代地更新初始OPC掩模图案以生成输出的最终OPC掩模图案。

公开(公告)号：US20150339429A1

公开(公告)日：2015-11-26

申请号：US14285739

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yi Zou ,  Wei-Long Wang ,  Azat Latypov ,  Tamer Coskun

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括在设计布局中标识DSA目标图案的位置。 DSA目标模式被分组成包括第一组的组，并且围绕第一组定义第一组边界。 所述方法还包括确定到所述第一组边界的相邻DSA目标图案是否是距离在所述第一组边界内的相邻DSA目标图案至少预定的最小保持距离。 该方法还包括确定第一组中的DSA目标模式是否兼容DSA。 使用第一组边界生成输出掩模图案。

公开(公告)号：US09305800B2

公开(公告)日：2016-04-05

申请号：US14185491

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Tamer Coskun ,  Wei-Long Wang ,  Azat Latypov ,  Yi Zou

IPC: H01L21/308 ,  H01L21/027

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0274 ,  H01L21/308

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖在半导体衬底上的辅助抗蚀刻填充形貌特征，并且使用光掩模来定义辅助耐蚀刻填充约束阱。 光掩模定义了辅助的可光刻印刷的掩模特征。 将嵌段共聚物沉积到辅助抗蚀填充密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 辅助抗蚀刻填充形貌特征指示耐腐蚀相以在辅助耐蚀刻填充密封阱中形成耐蚀刻塞。

公开(公告)号：US20150242555A1

公开(公告)日：2015-08-27

申请号：US14189465

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei-Long Wang ,  Azat Latypov ,  Yi Zou ,  Tamer Coskun

IPC: G06F17/50 ,  H01L21/311 ,  H01L21/027

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  H01L21/0271 ,  H01L21/0274 ,  H01L21/31133

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括输入DSA目标图案。 DSA目标图案被分组成包括第一组的组，并且组边界围绕第一组被定义为初始OPC掩模模式。 围绕第一组中的每个DSA目标图案生成圆目标以定义合并的圆目标边界。 使用合并的圆目标边界来调整和/或迭代地更新初始OPC掩模图案以生成输出的最终OPC掩模图案。

公开(公告)号：US20140220786A1

公开(公告)日：2014-08-07

申请号：US13757286

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Todd Lukanc ,  Christopher Heinz Clifford ,  Tamer Coskun

IPC: G06F17/50 ,  H01L21/02

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  H01L21/02348 ,  Y10S438/942 ,  Y10S438/948

Abstract: A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.

Abstract translation: 制造光学光刻掩模的方法包括提供包括多个多边形的图案化布局设计，通过调整多个多边形中的一个或多个的多边形的宽度和长度来使用光学邻近校正（OPC）校正图案化布局设计，以产生 校正的图案布局设计，将校正的图案布局设计转换成掩模写入器兼容格式，以生成包括多个多边形的掩模写入器兼容的布局设计，并且利用大的多边形偏置多边形中的每个多边形 - 图案布局设计的尺度密度值，以产生偏置的掩模写入器兼容布局设计。