公开(公告)号：US10062711B2

公开(公告)日：2018-08-28

申请号：US15386507

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Shank ,  Alvin Joseph ,  Michel Abou-Khalil ,  Michael Zierak

IPC: H01L27/12 ,  H01L21/00 ,  H01L21/84 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L21/762 ,  H01L21/683

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2221/6835

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

公开(公告)号：US20180175064A1

公开(公告)日：2018-06-21

申请号：US15386507

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Shank ,  Alvin Joseph ,  Michel Abou-Khalil ,  Michael Zierak

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L21/762 ,  H01L21/84 ,  H01L21/683

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/4238 ,  H01L2221/6835

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

公开(公告)号：US20180204926A1

公开(公告)日：2018-07-19

申请号：US15921715

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US09978849B2

公开(公告)日：2018-05-22

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US09721948B1

公开(公告)日：2017-08-01

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

公开(公告)号：US20170221882A1

公开(公告)日：2017-08-03

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

公开(公告)号：US20170186845A1

公开(公告)日：2017-06-29

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.