公开(公告)号：US09324822B2

公开(公告)日：2016-04-26

申请号：US14321679

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/423 ,  H01L21/66 ,  H01L29/08 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  G01R31/26

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Abstract translation: 本文公开的至少一种方法，装置和系统包括形成包括晶体管的器件，晶体管包括与有源栅极并联的至少一个非活性栅极。 形成基板上的源极区域。 在邻近源极区域的衬底上形成有源栅极区域。 在邻近有源栅极区的衬底上形成漏极区。 第一非活性栅极区域平行于有源栅极区域形成在衬底上。 源极区域，漏极区域，有源栅极区域和第一非活性栅极区域包括晶体管。 第一非活性栅极区域能够耗散电荷的至少一部分。

公开(公告)号：US20150346271A1

公开(公告)日：2015-12-03

申请号：US14288278

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/26 ,  G01R31/12

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

Abstract translation: 本文公开的至少一种方法和系统涉及在器件上执行时间依赖介电击穿（TDDB）测试和偏置温度不稳定性（BTI）测试。 提供具有至少一个晶体管和至少一个电介质层的器件。 提供测试信号用于在设备上执行TDDB测试和BTI测试。 基于测试信号，在设备上基本上同时执行TDDB测试和BTI测试。 获取，存储和/或发送与介电层的击穿和基于TDDB测试和BTI测试的晶体管的至少一个特性相关的数据。

公开(公告)号：US20170292986A1

公开(公告)日：2017-10-12

申请号：US15625609

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/12 ,  G01R31/26 ,  G01R31/28

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US09702926B2

公开(公告)日：2017-07-11

申请号：US14288278

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/26 ,  G01R31/12

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US10126354B1

公开(公告)日：2018-11-13

申请号：US15635711

申请日：2017-06-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andreas Kerber ,  Tanya Nigam ,  Fernando Guarin

IPC: G01R31/26 ,  G01R31/28 ,  H01L27/092 ,  H01L27/118

Abstract: CMOS switching devices are connected to testing equipment that applies AC to stress the CMOS switching devices. The testing equipment varies rise and fall times of drain and gate voltages, and varies offsets of the drain and gate voltages of the CMOS switching devices. The amount of hot carrier injection (HCI) within the CMOS switching devices is measured when the rise and fall times of the drain and gate voltages cross over, to establish AC HCI contribution to device degradation of the CMOS switching devices. Further, these methods can correlate the AC HCI contribution of the CMOS switching devices to CMOS logic devices based on ring oscillator (RO) degradation of ROs similarly tested or simulated, to produce AC HCI contribution for the CMOS logic devices.

公开(公告)号：US20160005828A1

公开(公告)日：2016-01-07

申请号：US14321679

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  G01R31/26 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/66 ,  H01L21/762

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Abstract translation: 本文公开的至少一种方法，装置和系统包括形成包括晶体管的器件，晶体管包括与有源栅极并联的至少一个非活性栅极。 形成基板上的源极区域。 在邻近源极区域的衬底上形成有源栅极区域。 在邻近有源栅极区的衬底上形成漏极区。 第一非活性栅极区域平行于有源栅极区域形成在衬底上。 源极区域，漏极区域，有源栅极区域和第一非活性栅极区域包括晶体管。 第一非活性栅极区域能够耗散电荷的至少一部分。

公开(公告)号：US10054630B2

公开(公告)日：2018-08-21

申请号：US15625609

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/26 ,  G01R31/12 ,  G01R31/28

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US09599656B2

公开(公告)日：2017-03-21

申请号：US14553863

申请日：2014-11-25

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon ,  Eduard A. Cartier

IPC: G01R31/00 ,  G01R31/14 ,  G01R31/28

CPC classification number: G01R31/14 ,  G01R31/2879

Abstract: At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.

公开(公告)号：US20160204098A1

公开(公告)日：2016-07-14

申请号：US15080090

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L27/02 ,  H01L21/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

公开(公告)号：US20140110772A1

公开(公告)日：2014-04-24

申请号：US14075517

申请日：2013-11-08

Applicant: Globalfoundries, Inc.

Inventor： Andreas Kerber ,  Tanya Nigam ,  Dieter Lipp ,  Marc Herden

IPC: H01L27/06

CPC classification number: H01L27/06 ,  H01L27/0629 ,  H01L27/0805

Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.

Abstract translation: 为集成电路提供去耦电容器布置。 该装置包括彼此并联电连接的多个去耦电容器阵列。 每个阵列包括多个去耦电容器和限流元件。 每个阵列的去耦电容彼此并联电连接。 限流元件与多个去耦电容器串联连接。