公开(公告)号：US10096595B2

公开(公告)日：2018-10-09

申请号：US15286196

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain ,  Anurag Mittal ,  Sangmoon Kim

IPC: H01L27/02 ,  H01L27/06 ,  G06F17/50 ,  H01L27/11 ,  H01L29/66

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

公开(公告)号：US08751985B1

公开(公告)日：2014-06-10

申请号：US13795198

申请日：2013-03-12

Applicant: Globalfoundries Inc.

Inventor： Sandeep Puri ,  Bipul C. Paul ,  Werner Juengling ,  Anurag Mittal

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Hierarchical layout versus schematic comparison with extraneous device elimination is provided. This includes obtaining a hierarchical layout netlist for a circuit design, the hierarchical layout netlist grouping arrayed devices of the circuit design into blocks repeated at a top level of a hierarchy of the hierarchical layout netlist. A modified hierarchical layout netlist defining active devices and connections thereof to top level pads of the circuit design is generated, in which extraneous devices are selectively removed from the obtained hierarchical layout netlist. The modified hierarchical layout netlist is verified against an input schematic netlist defining active devices of the circuit design and connections thereof to pads of the circuit design.

Abstract translation: 提供了层次布局与与外部设备消除的原理图比较。 这包括获得用于电路设计的分层布局网表，分层布局网表将电路设计的阵列设备分组成在分级布局网表的层次结构的顶层重复的块。 产生了将有源器件及其连接定义为电路设计的顶级焊盘的修改的分层布局网表，其中从获得的分层布局网表中选择性地移除了外来设备。 修改的分层布局网表针对定义电路设计的有源器件的输入原理图网表及其与电路设计的焊盘的连接来验证。

公开(公告)号：US20190148245A1

公开(公告)日：2019-05-16

申请号：US15810557

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

CPC classification number: H01L21/823871 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/4941 ,  H01L2924/0002

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

公开(公告)号：US20170063357A1

公开(公告)日：2017-03-02

申请号：US14838215

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anurag Mittal ,  Mahbub Rashed

IPC: H03K5/14 ,  H03K19/0185 ,  G06F17/50

CPC classification number: H03K5/14 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/84 ,  H03K5/133 ,  H03K19/01855 ,  H03K2005/00019

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. An operation modeling of a semiconductor device circuit design is performed. At least one transistor is identified for providing at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing the transistor. Selectively providing a delay for adjusting a timing associated with the transistor based upon identifying the at least one transistor for providing the at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing.

Abstract translation: 所公开的至少一种方法，装置和系统涉及提供用于制造半导体器件的设计。 执行半导体器件电路设计的操作建模。 识别至少一个晶体管用于提供用于正向偏置晶体管的第一电压或用于反向偏置晶体管的第二电压中的至少一个。 基于识别用于提供用于正向偏置晶体管的第一电压或用于反向偏置的第二电压的至少一个晶体管，选择性地提供用于调整与晶体管相关联的定时的延迟。

公开(公告)号：US09293414B2

公开(公告)日：2016-03-22

申请号：US14551249

申请日：2014-11-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： O Sung Kwon ,  Xiaoqiang Zhang ,  Anurag Mittal

IPC: H01L23/522 ,  H01L29/00 ,  H01L27/06 ,  H01L27/108 ,  H01L23/525 ,  H01L23/367 ,  H01L23/532 ,  H01L27/10

CPC classification number: H01L23/5256 ,  H01L23/3677 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0629 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse includes a body, an anode coupled to the body, and a cathode coupled to the body. Each of the anode and the cathode includes a first line contacting the body. The first line is discontinuous along its length and includes a first portion and a second portion with a space therebetween. A second line is disposed above the first line and a plurality of vias couple the first and second lines. The first portion of the first line is coupled to a first subset of the plurality of vias and the second portion of the first line is coupled to a second subset of the vias.

Abstract translation: 电子熔断器包括主体，耦合到主体的阳极和耦合到主体的阴极。 阳极和阴极中的每一个包括接触身体的第一线。 第一线沿其长度是不连续的，并且包括第一部分和第二部分之间的空间。 第二线设置在第一线上方，并且多个通孔耦合第一线和第二线。 第一行的第一部分耦合到多个通孔的第一子集，并且第一行的第二部分耦合到通孔的第二子集。

公开(公告)号：US20150145059A1

公开(公告)日：2015-05-28

申请号：US14581171

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： O Sung Kwon ,  Xiaoqiang Zhang ,  Anurag Mittal

IPC: H01L27/06 ,  H01L23/532 ,  H01L49/02 ,  H01L23/525

CPC classification number: H01L27/0629 ,  H01L21/76889 ,  H01L23/5225 ,  H01L23/5256 ,  H01L23/53261 ,  H01L27/101 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials.

Abstract translation: 公开了一种集成电路产品，其包括位于接触电介质材料上的电阻体和电熔体，其中电阻体和电熔体体由相同的导电材料制成，第一多个导电接触结构 耦合到电阻器主体，导电阳极和阴极结构导电地耦合到电熔体本体，其中第一多个导电接触结构和导电阳极和阴极结构由相同的材料制成。

公开(公告)号：US09263385B1

公开(公告)日：2016-02-16

申请号：US14589011

申请日：2015-01-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Anurag Mittal

IPC: H01L23/525 ,  H01L23/538 ,  H01L21/62 ,  H01L21/71 ,  H01L27/24 ,  H01L21/768 ,  H01L29/417 ,  H01L29/45 ,  H01L29/8605 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L21/823431 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor fuses with epitaxial fuse link regions and fabrication methods thereof are presented. The methods include: fabricating a semiconductor fuse including an anode region and a cathode region electrically linked by a fuse link region, and the fabricating including: forming, epitaxially, the fuse link region between the anode region and the cathode region, wherein the fuse link region facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region thereof. The semiconductor fuses include: an anode region and a cathode region electrically linked by a fuse link region, wherein the fuse link region includes an epitaxial structure and facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region, wherein the epitaxial structure is in at least partial crystallographic alignment with the anode region and the cathode region of the semiconductor fuse.

Abstract translation: 提出了具有外延熔丝链接区域的半导体熔丝及其制造方法。 所述方法包括：制造包括通过熔丝链区域电连接的阳极区域和阴极区域的半导体熔丝，所述制造方法包括：外延地形成阳极区域和阴极区域之间的熔断体区域，其中熔丝连接 区域有助于半导体熔丝开路，以在阳极区域和阴极区域之间施加编程电流。 半导体熔丝包括：通过熔丝链区域电连接的阳极区域和阴极区域，其中熔丝链路区域包括外延结构，并且有助于半导体熔丝开路以在阳极区域和阴极区域之间施加编程电流， 其中所述外延结构与半导体保险丝的阳极区域和阴极区域至少部分晶体取向。

公开(公告)号：US08981492B2

公开(公告)日：2015-03-17

申请号：US13928060

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： O Sung Kwon ,  Xiaoqiang Zhang ,  Anurag Mittal

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L23/525 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/76889 ,  H01L23/5225 ,  H01L23/5256 ,  H01L23/53261 ,  H01L27/101 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials.

Abstract translation: 公开了一种集成电路产品，其包括位于接触电介质材料上的电阻体和电熔体，其中电阻体和电熔体体由相同的导电材料制成，第一多个导电接触结构 耦合到电阻器主体，导电阳极和阴极结构导电地耦合到电熔体本体，其中第一多个导电接触结构和导电阳极和阴极结构由相同的材料制成。

公开(公告)号：US20140264731A1

公开(公告)日：2014-09-18

申请号：US13833934

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andrew Kim ,  O Sung Kwon ,  Xiaoqiang Zhang ,  Seung-Hyun Rhee ,  Anurag Mittal

IPC: H01L23/525 ,  H01L23/34

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative e-fuse device disclosed herein includes first and second conductive structures, a first electrically conductive heat cage element that is conductively coupled to the first conductive structure, wherein the first heat cage element is adapted to carry an electrical current, a second electrically conductive heat cage element that is conductively coupled to the second conductive structure, wherein the second heat cage element is adapted to carry the electrical current, and a programmable, electrically conductive e-fuse element that is conductively coupled to each of the first and second electrically conductive heat cage elements and adapted to carry the electrical current, wherein the e-fuse element is positioned adjacent to each of the first and second electrically conductive heat cage elements.

Abstract translation: 本文公开的一个示例性电熔丝装置包括第一和第二导电结构，第一导电加热笼元件，其导电耦合到第一导电结构，其中第一加热笼元件适于承载电流，第二导电 导热耦合到所述第二导电结构的热笼形元件，其中所述第二加热笼元件适于承载电流;以及可编程的导电电熔丝元件，其导电地耦合到所述第一和第二导电 加热笼形元件并且适于承载电流，其中所述电熔丝元件邻近所述第一和第二导电加热笼元件中的每一个定位。

公开(公告)号：US20140021579A1

公开(公告)日：2014-01-23

申请号：US14032484

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

Abstract translation: 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。