公开(公告)号：US09490223B2

公开(公告)日：2016-11-08

申请号：US14566773

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L21/70 ,  H01L23/00 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

Abstract translation: 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。

公开(公告)号：US10403772B2

公开(公告)日：2019-09-03

申请号：US15886927

申请日：2018-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao Li ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang ,  Joseph Ervin

IPC: G02B6/12 ,  H01L31/0232 ,  H01L23/48 ,  G02B6/42 ,  G02B6/43 ,  G02B6/122 ,  H01L31/02 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

公开(公告)号：US09461042B2

公开(公告)日：2016-10-04

申请号：US14746017

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

公开(公告)号：US20160116435A1

公开(公告)日：2016-04-28

申请号：US14987329

申请日：2016-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: G01N27/414 ,  H01L29/08

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米级串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

公开(公告)号：US09478600B2

公开(公告)日：2016-10-25

申请号：US14175587

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

公开(公告)号：US20160172314A1

公开(公告)日：2016-06-16

申请号：US14566773

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L23/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

Abstract translation: 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。

公开(公告)号：US09343320B2

公开(公告)日：2016-05-17

申请号：US14098650

申请日：2013-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L27/108 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/84 ,  H01L29/66 ,  H01L29/94 ,  H01L27/12

CPC classification number: H01L21/30604 ,  H01L21/3081 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench.

Abstract translation: 虚拟深沟槽可以形成在其中将在存储器件区域内形成深沟槽电容器的逻辑器件区域内形成逻辑器件。 半导体翅片在形成沟槽之前形成在顶表面上，并且一次性材料填充在所述半导体鳍片周围。 所述一次性填充材料层的顶表面可以与所述半导体鳍片的顶表面共面，这使得深沟槽形成更容易。 虚拟深沟槽的导电材料部分可以凹入以避免与逻辑器件区域内的半导体鳍片的电接触，而每个深沟槽的内部电极可接触存储器件区域内的半导体鳍片。 可以在虚拟深沟槽的每个导电材料部分上方形成电介质材料部分。

公开(公告)号：US09228994B1

公开(公告)日：2016-01-05

申请号：US14452741

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/40 ,  G01N33/487 ,  H01L27/088 ,  H01L29/66 ,  H01L29/41

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米尺度串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

公开(公告)号：US09929290B2

公开(公告)日：2018-03-27

申请号：US15187048

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao Li ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang ,  Joseph Ervin

IPC: G02B6/12 ,  H01L31/0232 ,  H01L23/48 ,  H01L31/02 ,  G02B6/122 ,  G02B6/42

CPC classification number: H01L31/02327 ,  G02B6/122 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12123 ,  H01L21/76898 ,  H01L23/481 ,  H01L31/02005

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

公开(公告)号：US09557290B2

公开(公告)日：2017-01-31

申请号：US14987329

申请日：2016-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/08 ,  G01N27/414 ,  G01N33/487 ,  H01L29/41 ,  H01L21/84 ,  H01L27/12

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米级串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。