公开(公告)号：US20160049327A1

公开(公告)日：2016-02-18

申请号：US14459444

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil Kumar SINGH ,  Ravi Prakash SRIVASTAVA ,  Teck Jung TANG ,  Mark Alexander ZALESKI

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).

Abstract translation: 提供了用于制造用于例如为电路结构提供BEOL互连的层间结构的方法。 该方法包括例如提供层间结构，包括：在衬底结构之上提供未固化的绝缘层; 在未固化的绝缘层上形成能量去除膜; 通过所述能量去除膜形成至少一个开口并且至少部分地延伸到所述未固化的绝缘层中; 并施加能量以固化未固化绝缘层，建立固化绝缘层，并部分分解能量去除膜，在固化绝缘层上形成厚度减小的能量去除膜，包括固化绝缘层的层间结构，以及 施加减小一个开口的纵横比的能量。 在一个实施方案中，未固化的绝缘层包括在施加能量的同时分解部分以进一步改善纵横比的致孔剂。

公开(公告)号：US20170178953A1

公开(公告)日：2017-06-22

申请号：US14978650

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Sohan Singh MEHTA ,  Ravi Prakash SRIVASTAVA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76817 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528

Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170186688A1

公开(公告)日：2017-06-29

申请号：US15460976

申请日：2017-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Ravi Prakash SRIVASTAVA ,  Nicholas Robert STOKES

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/288 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170047290A1

公开(公告)日：2017-02-16

申请号：US14824181

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil Kumar SINGH ,  Ravi Prakash SRIVASTAVA ,  Nicholas Robert STOKES

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

Abstract translation: 用于半导体器件的金属填充工艺和制造半导体器件的方法。 一种方法包括例如：获得具有至少一个接触开口的晶片; 将金属合金沉积到所述至少一个接触开口的至少一部分中; 将金属合金分离成第一金属层和第二金属层; 在晶片上沉积势垒堆叠; 形成至少一个沟槽开口; 形成至少一个通孔; 以及将至少一种金属材料沉积到沟槽开口和通孔中。 还公开了一种中间半导体器件。