公开(公告)号：US09390928B2

公开(公告)日：2016-07-12

申请号：US14059842

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Hari V. Mallela ,  Reinaldo Vega

IPC: H01L21/28 ,  H01L29/772 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/28008 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/772

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

Abstract translation: 可以增强栅极电极和源极和漏极区域的下部之间的电容耦合，同时抑制栅极电极和横向间隔开的元件之间的电容耦合，例如用于源极和漏极区域的接触通孔结构。 使用一次性栅极间隔物形成包括栅极和源极和漏极区的晶体管。 去除一次性栅极间隔物以形成间隔腔，其填充有各向异性介电材料以形成各向异性栅极间隔物。 各向异性介电材料与电场对准，使得各向异性介电材料的分子的纵向方向在间隔空腔内垂直排列。 各向异性栅极间隔沿垂直方向提供较高介电常数，沿水平方向提供较低介电常数。

公开(公告)号：US09875939B1

公开(公告)日：2018-01-23

申请号：US15373129

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yue Ke ,  Alexander Reznicek ,  Benjamin Moser ,  Dominic J. Schepis ,  Melissa A. Smith ,  Henry K. Utomo ,  Reinaldo Vega ,  Sameer Jain

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/266 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66795

Abstract: Methods of fabricating integrated circuit devices for forming uniform and well controlled fin recesses are disclosed. One method includes, for instance: obtaining an intermediate semiconductor structure having a substrate, at least one fin disposed on the substrate, at least one gate structure positioned over the at least one fin, and at least one oxide layer disposed on the substrate and about the at least one fin and the at least one gate structure; implanting germanium (Ge) in a first region of the at least one fin; and removing the first region of the at least one fin implanted with Ge.