公开(公告)号：US09947532B2

公开(公告)日：2018-04-17

申请号：US15425338

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

公开(公告)号：US09287264B1

公开(公告)日：2016-03-15

申请号：US14561395

申请日：2014-12-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. T. Harley ,  Judson R. Holt ,  Gauri V. Karve ,  Yue Ke ,  Derrick Liu ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L29/36 ,  H01L29/20 ,  H01L29/16 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract translation: 本发明的实施例提供了一种外延生长FinFET的方法。 一种方法可以包括提供包括绝缘体和底层的半导体衬底; 使用外延生长在所述半导体衬底上形成沟道层; 将凹槽蚀刻到沟道层中并外延地再生沟道层上的一部分; 蚀刻通道层和底层以形成翅片; 形成栅极结构和一组间隔物; 将源漏区蚀刻到沟道层中; 以及在源极漏极区域中形成源极漏极材料。

公开(公告)号：US09875939B1

公开(公告)日：2018-01-23

申请号：US15373129

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yue Ke ,  Alexander Reznicek ,  Benjamin Moser ,  Dominic J. Schepis ,  Melissa A. Smith ,  Henry K. Utomo ,  Reinaldo Vega ,  Sameer Jain

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/266 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66795

Abstract: Methods of fabricating integrated circuit devices for forming uniform and well controlled fin recesses are disclosed. One method includes, for instance: obtaining an intermediate semiconductor structure having a substrate, at least one fin disposed on the substrate, at least one gate structure positioned over the at least one fin, and at least one oxide layer disposed on the substrate and about the at least one fin and the at least one gate structure; implanting germanium (Ge) in a first region of the at least one fin; and removing the first region of the at least one fin implanted with Ge.

公开(公告)号：US20160181359A1

公开(公告)日：2016-06-23

申请号：US14578523

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/304 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.

Abstract translation: 一种半导体结构，包括：沟槽限定层; 外延层; 和一组缺陷阻挡构件。 沟槽限定层包括限定被称为“沟槽”的细长内部空间的沟槽表面。外延层在沟槽的内部空间中外延生长。 该组缺陷阻挡构件的每个缺陷阻挡构件：（i）从沟槽表面的一部分延伸到沟槽的内部空间中; 和（ii）位于外延层的顶表面下方。 缺陷阻挡构件设计成在其生长时阻止外延层中的大致纵向缺陷的传播，其中大致纵向缺陷是至少大体上在沟槽的伸长方向上传播的缺陷。

公开(公告)号：US09589965B1

公开(公告)日：2017-03-07

申请号：US15004216

申请日：2016-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Melissa A. Smith ,  Sunit S. Mahajan ,  Herbert L. Ho

IPC: H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10879

Abstract: Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in a substrate. An epitaxy-retarding dopant is introduced to an upper portion of the trenches. A plurality of fins are then formed over the substrate, with each polysilicon-filled deep trench including a corresponding fin extending thereover. A silicon layer is epitaxially grown over at least the polysilicon-filled deep trench. The dopant in the polysilicon-filled deep trenches acts to control the epitaxial growth of the silicon layer, diminishing or preventing shorts to adjacent fins and/or deep trenches at advanced technology nodes.

Abstract translation: 提供了形成用于eDRAM的多晶硅填充深沟槽的方法。 该方法可以包括在衬底中形成多个多晶硅填充的深沟槽。 将外延延迟掺杂剂引入到沟槽的上部。 然后在衬底上形成多个翅片，其中每个多晶硅填充的深沟槽包括在其上延伸的对应的鳍。 至少在多晶硅填充的深沟槽上外延生长硅层。 在多晶硅填充的深沟槽中的掺杂剂用于控制硅层的外延生长，减少或防止在先进技术节点处的相邻鳍片和/或深沟槽的短路。

公开(公告)号：US20170148661A1

公开(公告)日：2017-05-25

申请号：US15425338

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L21/76 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

公开(公告)号：US09601565B2

公开(公告)日：2017-03-21

申请号：US14578523

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L29/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.