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    Methods of forming contact structures for semiconductor devices and the resulting devices
    3.
    发明授权
    Methods of forming contact structures for semiconductor devices and the resulting devices 有权
    形成用于半导体器件和所得器件的接触结构的方法

    公开(公告)号：US09330972B2

    公开(公告)日：2016-05-03

    申请号：US14457708

    申请日：2014-08-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Vimal Kamineni ,  William J. Taylor, Jr.

    IPC: H01L27/12 ,  H01L21/84 ,  H01L21/425 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/4975 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41758 ,  H01L29/78 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material.

    Abstract translation: 本文公开的一种方法包括形成与晶体管器件的源极/漏极区域的接触结构的方法。 晶体管器件包括栅极结构和位于栅极结构上方的栅极帽层。 该方法包括形成导电耦合到源极/漏极区的扩展高度外延接触结构。 所述延伸高度外延接触结构包括位于所述栅极盖层的上表面的高度以上的高度水平处的上表面。 该方法还包括执行蚀刻工艺以修剪延伸高度外延接触结构的一部分的至少横向宽度，并且在执行蚀刻工艺之后，在修剪的延伸高度外延接触结构的至少一部分上形成金属硅化物材料， 高度epi接触结构，并在金属硅化物材料上形成导电接触。

    Semiconductor device having a metal gate recess
    4.
    发明授权
    Semiconductor device having a metal gate recess 有权
    具有金属栅极凹槽的半导体器件

    公开(公告)号：US08890262B2

    公开(公告)日：2014-11-18

    申请号：US13688259

    申请日：2012-11-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal Kamineni ,  Ruilong Xie

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00 ,  H01L29/49 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

    Abstract translation: 提供了在沟槽（例如，通过CVD和/或ALD）中具有衬里层和金属层（例如钨（W））的半导体器件（例如，诸如FinFET或平面器件的晶体管）。 将使用单个室（例如，极端填充室）来单独地蚀刻衬里层和金属层。 通常，衬里层可以比金属层更深地被回蚀以提供较大的接触和较低的电阻。 蚀刻完成后，将执行金属（例如W）的自底向上填充/生长（例如，通过在W室等中的CVD）以增加沟槽中的栅极金属的存在。

    Devices and methods of cobalt fill metallization
    6.
    发明授权
    Devices and methods of cobalt fill metallization 有权

    公开(公告)号：US10128151B2

    公开(公告)日：2018-11-13

    申请号：US15381826

    申请日：2016-12-16

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal Kamineni ,  James Kelly ,  Praneet Adusumilli ,  Oscar Van Der Straten ,  Balasubramanian Pranatharthiharan

    IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532

    Abstract: Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (Co) layer on the second layer, and performing an anneal reflow process on the device. Also provided are intermediate semiconductor devices. An intermediate semiconductor device includes, for instance, at least one trench formed within the device, the trench having a bottom portion and sidewalls, at least one layer of semiconductor material disposed on the device, a first cobalt (Co) layer disposed on the at least one layer of semiconductor material, wherein the at least one layer of semiconductor material includes at least a first semiconductor material and a second semiconductor material.

    Methods for fabricating integrated circuits with improved contact structures
    8.
    发明授权
    Methods for fabricating integrated circuits with improved contact structures 有权
    具有改进的接触结构的集成电路的制造方法

    公开(公告)号：US09040421B2

    公开(公告)日：2015-05-26

    申请号：US13887174

    申请日：2013-05-03

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

    IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48

    CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.

    Abstract translation: 提供了制造集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括提供在其中和/或其上设置有器件的半导体衬底。 包括阻挡层和覆盖阻挡层的插塞金属的接触结构形成为与器件电接触。 覆盖接触结构的硬掩模形成。 该方法包括执行蚀刻以形成通过硬掩模的通孔，并暴露阻挡层和插塞金属。 此外，该方法用湿蚀刻剂去除硬掩模的剩余部分，而接触结构被配置为抑制湿蚀刻剂蚀刻阻挡层。 在该方法中，通孔开口填充有导电材料以形成与接触结构的互连。

    METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS
    9.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS 有权
    用于形成具有金属门盖的半导体器件的方法

    公开(公告)号：US20150056796A1

    公开(公告)日：2015-02-26

    申请号：US14514422

    申请日：2014-10-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal Kamineni ,  Ruilong Xie

    IPC: H01L29/40 ,  H01L29/49

    CPC classification number: H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Provided are approaches of forming a semiconductor device (e.g., transistor such as a FinFET or planar device) having a gate metal recess. In one approach, a liner layer and a metal layer (e.g., W) are applied in a trench (e.g., via CVD and/or ALD). Then, a single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

    Abstract translation: 提供了形成具有栅极金属凹部的半导体器件（例如，诸如FinFET或平面器件的晶体管）的方法。 在一种方法中，将衬垫层和金属层（例如，W）施加在沟槽（例如，经由CVD和/或ALD）中。 然后，将使用单个室（例如，极端填充室）来单独地蚀刻衬里层和金属层。 通常，衬里层可以比金属层更深地被回蚀以提供较大的接触和较低的电阻。 蚀刻完成后，将执行金属（例如W）的自底向上填充/生长（例如，通过在W室等中的CVD）以增加沟槽中的栅极金属的存在。

    SEMICONDUCTOR DEVICE HAVING A METAL RECESS
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A METAL RECESS 有权
    具有金属接合的半导体器件

    公开(公告)号：US20140145257A1

    公开(公告)日：2014-05-29

    申请号：US13688259

    申请日：2012-11-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Vimal Kamineni ,  Ruilong Xie

    IPC: H01L29/49 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

    Abstract translation: 提供了在沟槽（例如，通过CVD和/或ALD）中具有衬里层和金属层（例如钨（W））的半导体器件（例如，诸如FinFET或平面器件的晶体管）。 将使用单个室（例如，极端填充室）来单独地蚀刻衬里层和金属层。 通常，衬里层可以比金属层更深地被回蚀以提供较大的接触和较低的电阻。 蚀刻完成后，将执行金属（例如W）的自底向上填充/生长（例如，通过在W室等中的CVD）以增加沟槽中的栅极金属的存在。

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