公开(公告)号：US10446550B2

公开(公告)日：2019-10-15

申请号：US15783549

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US10269932B1

公开(公告)日：2019-04-23

申请号：US15874341

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ankur Arya ,  Brian Greene ,  Qun Gao ,  Christopher Nassar ,  Junsic Hong ,  Vishal Chhabra

IPC: H01L27/01 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: One illustrative method disclosed herein includes, among other things, forming a first fin having first and second opposing sidewalls and forming a first sidewall spacer positioned adjacent the first sidewall and a second sidewall spacer positioned adjacent the second sidewall, wherein the first sidewall spacer has a greater height than the second sidewall spacer. In this example, the method further includes forming epitaxial semiconductor material on the fin and above the first and second sidewall spacers.

公开(公告)号：US10658363B2

公开(公告)日：2020-05-19

申请号：US16562481

申请日：2019-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US10020260B1

公开(公告)日：2018-07-10

申请号：US15388530

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Benjamin G. Moser ,  Vimal Kumar Kamineni ,  Dinesh Koli ,  Vishal Chhabra

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/265 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.