公开(公告)号：US20200144106A1

公开(公告)日：2020-05-07

申请号：US16177854

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Chanro Park ,  Ruilong Xie ,  Andre P. Labonte

IPC: H01L21/768

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

公开(公告)号：US10388602B2

公开(公告)日：2019-08-20

申请号：US15251804

申请日：2016-08-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Vimal Kamineni ,  Andre P. Labonte ,  Ruilong Xie

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

公开(公告)号：US10332977B2

公开(公告)日：2019-06-25

申请号：US15880059

申请日：2018-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US09947589B1

公开(公告)日：2018-04-17

申请号：US15600874

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Lars W. Liebmann ,  Andre P. Labonte ,  Nigel G. Cave ,  Mark V. Raymond

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L21/823437 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76892 ,  H01L21/76895 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L23/535 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/785

Abstract: A transistor is formed above an active region. The transistor includes a gate structure, a first gate cap layer and a first sidewall spacer positioned adjacent sidewalls of the gate structure. Source/drain contacts are formed adjacent the first sidewall spacer. The first gate cap layer and a portion of the first sidewall spacer are removed to define a gate contact cavity that exposes a portion of the gate structure and an upper portion of the SD contacts. A second spacer and a conductive gate plug are formed in the gate contact cavity. Upper portions of the SD contacts positioned adjacent the second spacer are removed to define a gate cap cavity. A second gate cap layer is formed in the gate cap cavity. An insulating layer is formed above the second gate cap layer. A first conductive structure is formed in the insulating layer conductively coupled to the gate structure.

公开(公告)号：US09640625B2

公开(公告)日：2017-05-02

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L29/76 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

公开(公告)号：US20180286956A1

公开(公告)日：2018-10-04

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L29/41775 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66545

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

公开(公告)号：US09941163B2

公开(公告)日：2018-04-10

申请号：US15618880

申请日：2017-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66 ,  H01L23/535 ,  H01L27/11

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170170118A1

公开(公告)日：2017-06-15

申请号：US15251804

申请日：2016-08-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Vimal Kamineni ,  Andre P. Labonte ,  Ruilong Xie

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L23/535

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

公开(公告)号：US09570397B1

公开(公告)日：2017-02-14

申请号：US14964786

申请日：2015-12-10

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Vimal Kamineni ,  Andre P. Labonte ,  Ruilong Xie

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L23/535

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

Abstract translation: 局部互连结构包括具有电介质层和嵌入电介质层中的至少一个半导体接触结构的衬底。 导电材料沉积在限定至少一个导电接触通孔的非侵蚀接触沟槽中。 接触通孔从与电介质层的上表面齐平的第一端延伸到接触一个半导体接触结构的第二端。 在电介质层中形成局部导电材料层并接触接触通孔的第一端。 非侵蚀接触沟槽包括相对于接触通孔的第一端大致九十度形成的尖锐的上角。

公开(公告)号：US10790376B2

公开(公告)日：2020-09-29

申请号：US16105102

申请日：2018-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Julien Frougier ,  Kangguo Cheng ,  Andre P. Labonte

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/3213

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.