公开(公告)号：US09608086B2

公开(公告)日：2017-03-28

申请号：US14282257

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae G. Yang ,  Mariappan Hariharaputhiran ,  Jing Wan

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L27/1104 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

公开(公告)号：US20160005868A1

公开(公告)日：2016-01-07

申请号：US14320932

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Jing Wan ,  Dae-Han Choi

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Embodiments of the present invention provide a fin-type field effect transistor (finFET) with confined epitaxy. A protective layer is formed on a fin. The protective layer is recessed to expose the fin top. A fin cavity is formed in the fin. An epitaxial region is formed in the fin cavity. The epitaxial region has a confined portion and a diamond-shaped portion, resulting in increased epitaxial volume. The increased epitaxial volume can result in enhanced carrier mobility and improved device performance.

Abstract translation: 本发明的实施例提供了具有有限外延的翅片型场效应晶体管（finFET）。 在翅片上形成保护层。 保护层凹入以暴露翅片顶部。 翅片中形成翅片腔。 在翅片腔中形成外延区域。 外延区具有限制部分和菱形部分，导致增加的外延体积。 增加的外延体积可以导致增强的载流子迁移率和改进的器件性能。

公开(公告)号：US20170162688A1

公开(公告)日：2017-06-08

申请号：US15433330

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Dae G. Yang ,  Mariappan Hariharaputhiran ,  Jing Wan

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L27/1104 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

公开(公告)号：US09640625B2

公开(公告)日：2017-05-02

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L29/76 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

公开(公告)号：US09431512B2

公开(公告)日：2016-08-30

申请号：US14308257

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L21/336 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/775

Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

Abstract translation: 形成纳米线器件的方法包括在半导体衬底之上形成半导体材料层，在半导体材料层之上形成栅极结构，形成与栅极结构相邻的第一侧壁间隔物，并形成邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括使半导体材料层图案化，使得每个层具有第一和第二暴露的端表面。 栅极结构，第一侧壁间隔件和第二侧壁间隔件在图案化工艺期间被组合用作蚀刻掩模。 该方法还包括去除第一和第二侧壁间隔物，从而暴露图案化的半导体材料层的至少一部分。 该方法还包括在除去第一和第二侧壁间隔物之后，在至少图案化的半导体材料层的暴露部分中形成掺杂的延伸区域。

公开(公告)号：US09263520B2

公开(公告)日：2016-02-16

申请号：US14050494

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping Liu ,  Jing Wan ,  Andy Wei

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/66977 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

Abstract translation: 提出了用于促进半导体器件的制造的方法，例如栅极全能纳米线场效应晶体管。 所述方法包括例如：提供至少一个堆叠结构，其包括在衬底结构上方延伸的至少一个层或凸块; 选择性地氧化所述至少一个堆叠结构的至少一部分以形成至少一个纳米线，所述至少一个纳米线在由所述堆叠结构的氧化材料包围的所述堆叠结构内延伸; 以及从所述堆叠结构中去除所述氧化的材料，暴露所述纳米线。 这种选择性氧化可以包括氧化衬底结构的上部，例如支撑堆叠结构的一个或多个翅片的上部，以促进纳米线的完全360度曝光。 在一个实施例中，堆叠结构包括一个或多个菱形凸块或凸脊。

公开(公告)号：US20160049489A1

公开(公告)日：2016-02-18

申请号：US14457934

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jing Wan ,  Guillaume Bouche ,  Andy Wei ,  Shao Ming Koh

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Abstract translation: 提供了集成电路及其制造方法。 一种集成电路的制造方法，其特征在于，形成覆盖基板的分层散热片，其中层状散热片包括SiGe层和Si层。 SiGe层和Si层沿层状翅片的高度交替。 形成覆盖基板和分层翅片的虚拟栅极以及与层状翅片接触形成的源极和漏极区域。 去除伪栅极以暴露SiGe层和Si层，并且去除Si层以产生SiGe纳米线。 形成在源极和漏极之间封装SiGe纳米线的高K电介质层，并且形成替代金属栅极，使得替代金属栅极包围源极和漏极之间的高K电介质层和SiGe纳米线。

公开(公告)号：US20150340461A1

公开(公告)日：2015-11-26

申请号：US14282257

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc

Inventor： Andy Chih-Hung Wei ,  Dae G. Yang ,  Mariappan Hariharaputhiran ,  Jing Wan

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L27/1104 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

Abstract translation: 本发明的实施例提供一种金属栅极结构和形成方法。 在替代金属栅极（RMG）工艺流程中，栅极切割工艺在金属栅极形成之后进行。 这允许在门的末端和相邻鳍之间减小边缘。 它能够在虚拟栅极顶部形成更薄的牺牲层，因为栅极切割步骤被推迟。 更薄的牺牲层通过减少植入期间阴影的不利影响来提高器件质量。 此外，在该工艺流程中，功函数金属层通过封盖层沿着半导体衬底终止，这降低了在现有方法和结构中发生的阈值电压的不期望的移动。

公开(公告)号：US20150311082A1

公开(公告)日：2015-10-29

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L21/28 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

Abstract translation: 提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地说，栅极接触开口形成在一组栅极结构中的至少一个上，在半导体器件的鳍片之上形成一组S / D接触开口，并且在半导体器件上沉积金属材料以形成栅极 在门接触开口内接触一组S / D接触开口内的一组S / D接点。 在一种方法中，氮化物保留在栅极接触和至少一个S / D接触之间。 在另一种方法中，该装置包括合并门和S / D触点。 这种方法提供对分隔区域的选择性蚀刻，其中氧化物将被进一步选择性地去除氮化物以产生空穴以金属化并产生与S / D的接触，而接触区域之间的隔离区域被氮化物包围并且在氧化物蚀刻期间不被去除 。

公开(公告)号：US20150303295A1

公开(公告)日：2015-10-22

申请号：US14258279

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Xiang Hu ,  Jinping Liu ,  Gabriel Padron Wells ,  Andy Chih-Hung Wei ,  Guillaume Bouche ,  Cuiqin Xu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/51 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.

Abstract translation: 提供了在半导体器件（例如，FinFET器件）中形成一组接触开口的方法。 具体地，半导体器件包括形成在衬底中的一组翅片，形成在衬底上的栅极结构（例如，替换金属栅极（RMG））以及与栅极结构相邻的一组接触开口，该组接触 具有顶部和底部的开口，其中沿着栅极结构的长度的底部的宽度大于顶部的宽度。 半导体器件还包括形成在该组接触开口内的一组金属触头。