公开(公告)号：US20190057899A1

公开(公告)日：2019-02-21

申请号：US15678229

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Daniel JAEGER ,  Xusheng WU ,  Jinsheng GAO

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

公开(公告)号：US20200013672A1

公开(公告)日：2020-01-09

申请号：US16573209

申请日：2019-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng GAO ,  Daniel JAEGER ,  Chih-Chiang CHANG ,  Michael AQUILINO ,  Patrick CARPENTER ,  Junsic HONG ,  Mitchell RUTKOWSKI ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US20190237363A1

公开(公告)日：2019-08-01

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng GAO ,  Daniel JAEGER ,  Chih-Chiang CHANG ,  Michael AQUILINO ,  Patrick CARPENTER ,  Junsic HONG ,  Mitchell RUTKOWSKI ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US20180012760A1

公开(公告)日：2018-01-11

申请号：US15674763

申请日：2017-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui SHU ,  Daniel JAEGER ,  Garo Jacques DERDERIAN ,  Haifeng SHENG ,  Jinping LIU

IPC: H01L21/033 ,  H01L27/11

CPC classification number: H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.