公开(公告)号：US10790363B2

公开(公告)日：2020-09-29

申请号：US16054033

申请日：2018-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Kevin J. Ryan ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/66

Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

公开(公告)号：US10727136B2

公开(公告)日：2020-07-28

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US10699957B2

公开(公告)日：2020-06-30

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3105

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US20200168509A1

公开(公告)日：2020-05-28

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US20200152518A1

公开(公告)日：2020-05-14

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/40

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US20200052106A1

公开(公告)日：2020-02-13

申请号：US16101162

申请日：2018-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Neal Makela ,  Pei Liu ,  Jiehui Shu ,  Chih-chiang Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28

Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US20190341468A1

公开(公告)日：2019-11-07

申请号：US15971043

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/28

Abstract: A method includes forming a semiconductor device including a plurality of fins formed above a substrate, an isolation structure positioned between the plurality of fins, a plurality of sacrificial gate structures defining gate cavities, and a first dielectric material positioned between the sacrificial gate structures. A gate cut structure is formed in a first gate cavity. A trim etch process is performed to reduce a width of the gate cut structure. Replacement gate structures are formed in the gate cavities after performing the trim etch process. A first replacement gate structure in the first gate cavity is segmented by the gate cut structure.

公开(公告)号：US20190295898A1

公开(公告)日：2019-09-26

申请号：US16403745

申请日：2019-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311

Abstract: Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

公开(公告)号：US10388652B2

公开(公告)日：2019-08-20

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.