公开(公告)号：US09129987B2

公开(公告)日：2015-09-08

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jin Ping Liu ,  Guillaume Bouche ,  Andy Wei ,  Lakshmanan H. Vanamurthy ,  Cuiqin Xu ,  Sridhar Kuchibhatla ,  Rama Kambhampati ,  Xiuyu Cai

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧上沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US10741556B2

公开(公告)日：2020-08-11

申请号：US15719014

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

公开(公告)号：US09812453B1

公开(公告)日：2017-11-07

申请号：US15431334

申请日：2017-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.