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    Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures
    1.
    发明授权
    Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures 有权
    在IV族基底上形成III-V族半导体材料的方法和所得到的衬底结构

    公开(公告)号：US09275861B2

    公开(公告)日：2016-03-01

    申请号：US13927685

    申请日：2013-06-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Li Yang ,  Kejia Wang ,  Ashish Baraskar ,  Bin Yang ,  Shurong Liang

    IPC: H01L21/02 ,  H01L29/04 ,  H01L29/20

    CPC classification number: H01L21/02658 ,  H01L21/02373 ,  H01L21/0243 ,  H01L21/02538 ,  H01L29/045 ,  H01L29/20

    Abstract: One method disclosed herein includes forming a patterned mask layer above a surface of a semiconductor substrate, performing at least one etching process through the patterned mask layer to define a plurality of intersecting ridges that define a ridged surface in the substrate, and forming a Group III-V material on the ridged surface of the substrate. An illustrative device disclosed herein includes a Group IV substrate having a ridged surface comprised of a plurality of intersecting ridges and a Group III-V material layer positioned on the ridged surface of the Group IV substrate.

    Abstract translation: 本文公开的一种方法包括在半导体衬底的表面上形成图案化掩模层，通过图案化掩模层执行至少一个蚀刻工艺，以限定在衬底中限定脊状表面的多个相交脊，并形成第III组 -V在基板的脊状表面上的材料。 本文公开的说明性装置包括具有由多个相交脊组成的脊状表面的第IV族衬底和位于第IV族衬底的脊状表面上的III-V族材料层。

    Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process
    2.
    发明授权
    Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process 有权
    通过进行注入/退火缺陷生成工艺形成具有降低的缺陷密度的替代材料翅片

    公开(公告)号：US09224605B2

    公开(公告)日：2015-12-29

    申请号：US14267154

    申请日：2014-05-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

    IPC: H01L21/336 ,  H01L21/265 ,  H01L29/66 ,  H01L29/165 ,  H01L29/167 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78

    CPC classification number: H01L21/26513 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6681 ,  H01L29/7849

    Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

    Abstract translation: 公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在翅片沟槽中形成基本上无缺陷的半导体材料层，在第二层半导体材料上形成第二层半导体材料 形成第一半导体材料层的上表面，在第一半导体材料层和衬底之间的界面处形成注入区域，执行退火工艺以在至少第一半导体材料层中形成缺陷，形成 在所述第二半导体材料层上的第三层半导体材料，在所述第三半导体材料层上形成沟道半导体材料层，以及围绕所述沟道半导体材料的至少一部分形成栅极结构。

    Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device
    3.
    发明授权
    Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device 有权
    为FinFET半导体器件形成具有降低的缺陷密度的替代材料翅片的方法

    公开(公告)号：US09123627B1

    公开(公告)日：2015-09-01

    申请号：US14267010

    申请日：2014-05-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

    IPC: H01L29/165 ,  H01L29/66 ,  H01L29/36 ,  H01L21/306 ,  H01L21/322

    CPC classification number: H01L29/165 ,  H01L21/30608 ,  H01L21/3221 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785

    Abstract: One method disclosed herein includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming first and second layers of semiconductor material in the fin trench, after forming the second layer of semiconductor material, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, wherein, after the anneal process is performed, the upper surface of the second layer of semiconductor material is substantially defect-free, forming a layer of channel semiconductor material on the upper surface of the second layer of semiconductor material and forming a gate structure around at least a portion of the channel semiconductor material.

    Abstract translation: 本文公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在形成第二层半导体材料之后，在翅片沟槽中形成半导体材料的第一和第二层， 退火工艺以在至少第一半导体材料层中引起缺陷形成，其中，在进行退火处理之后，第二半导体材料层的上表面基本上是无缺陷的，在第二层上形成沟道半导体材料层 第二层半导体材料的上表面，并围绕沟道半导体材料的至少一部分形成栅极结构。

    FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY BY PERFORMING AN IMPLANTATION/ANNEAL DEFECT GENERATION PROCESS
    7.
    发明申请
    FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY BY PERFORMING AN IMPLANTATION/ANNEAL DEFECT GENERATION PROCESS 有权
    通过实施植入/缺陷生成过程形成具有减少缺陷密度的替代材料FINS

    公开(公告)号：US20150318176A1

    公开(公告)日：2015-11-05

    申请号：US14267154

    申请日：2014-05-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

    IPC: H01L21/265 ,  H01L29/165 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167

    CPC classification number: H01L21/26513 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6681 ,  H01L29/7849

    Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

    Abstract translation: 公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在翅片沟槽中形成基本上无缺陷的半导体材料层，在第二层半导体材料上形成第二层半导体材料 形成第一半导体材料层的上表面，在第一半导体材料层和衬底之间的界面处形成注入区域，执行退火工艺以在至少第一半导体材料层中形成缺陷，形成 在所述第二半导体材料层上的第三层半导体材料，在所述第三半导体材料层上形成沟道半导体材料层，以及围绕所述沟道半导体材料的至少一部分形成栅极结构。

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