公开(公告)号：US09966272B1

公开(公告)日：2018-05-08

申请号：US15632931

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haifeng Sheng ,  Haigou Huang ,  Tai Fong Chao ,  Jiehui Shu ,  Jinping Liu ,  Xingzhao Shi ,  Laertis Economikos

IPC: H01L21/00 ,  H01L21/3105

CPC classification number: H01L21/31056 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/823878

Abstract: The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.

公开(公告)号：US09865543B1

公开(公告)日：2018-01-09

申请号：US15416152

申请日：2017-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Haigou Huang ,  Stan Tsai ,  John H. Zhang ,  Xingzhao Shi ,  Tai Fong Chao

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/82 ,  H01L23/528 ,  H01L21/321 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L23/5283 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/53209

Abstract: A process for forming a conductive structure includes the formation of a self-aligned, inlaid conductive cap over a cobalt-based contact. The inlaid conductive cap is formed using a damascene process by depositing a conductive layer comprising tungsten or copper over a recessed cobalt-based contact, followed by a CMP step to remove excess portions of the conductive layer. The conductive cap can cooperate with a liner/barrier layer to form an effective barrier to cobalt migration and oxidation.

公开(公告)号：US20190326416A1

公开(公告)日：2019-10-24

申请号：US15956306

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Jiehui Shu ,  Chih-Chiang Chang ,  Xingzhao Shi ,  Jinsheng Gao ,  Huy Cao

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.

公开(公告)号：US10211103B1

公开(公告)日：2019-02-19

申请号：US15787257

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Dinesh Koli ,  Yuan Zhou ,  Xingzhao Shi ,  Chih-Chiang Chang ,  Tai Fong Chao

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

Abstract: Methods of forming a SAC cap with SiN U-shaped and oxide T-shaped structures and the resulting devices are provided. Embodiments include forming a substrate with a trench and a plurality of gate structures; forming a nitride liner over portions of the substrate and along sidewalls of each gate structure; forming an ILD between each gate structure and in the trench; recessing each gate structure between the ILD; forming a U-shaped nitride liner over each recessed gate structure; forming an a-Si layer over the nitride liner and the U-shaped nitride liner; removing portions of the nitride liner, the U-shaped nitride liner and the a-Si layer; forming a W layer over portions of the substrate adjacent to and between the a-Si layer; forming an oxide liner over the nitride liner, the U-shaped nitride liner and along sidewalls of the W layer; and forming an oxide layer over portions of the oxide liner.