公开(公告)号：US20160033958A1

公开(公告)日：2016-02-04

申请号：US14449222

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Stan Tsai ,  Charan V. V. S. Surisetty

IPC: G05B19/418

CPC classification number: B24B49/12 ,  B24B37/013 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

Abstract: Disclosed are approaches for determining a processing endpoint using individually measured target spectra. More specifically, one approach includes: measuring a white light (WL) target spectra of a semiconductor device on an individual wafer prior to formation of a polishing/planarization material; inputting the WL target spectra to a WL endpoint algorithm of the semiconductor device following formation of the polishing/planarization material; and determining, using the WL endpoint algorithm, the processing endpoint of the polishing/planarization material of the semiconductor device. In another approach, the endpoint measurement process comprises receiving spectra reflected from the semiconductor device during polishing, and comparing the spectra to the WL target spectra, which is previously stored within a storage device. As such, WL target spectra are measured “as is” (e.g., without simplifications, generalizations, assumptions, etc.) for each wafer to reduce complications inherent with the use of an uncertain and/or estimated target.

Abstract translation: 公开了使用单独测量的目标光谱确定处理端点的方法。 更具体地，一种方法包括：在形成抛光/平坦化材料之前测量单个晶片上的半导体器件的白光（WL）目标光谱; 在形成抛光/平坦化材料之后，将WL目标光谱输入到半导体器件的WL端点算法; 以及使用WL端点算法确定半导体器件的抛光/平坦化材料的处理端点。 在另一种方法中，端点测量过程包括在抛光期间接收从半导体器件反射的光谱，并将光谱与预先存储在存储器件中的WL目标光谱进行比较。 因此，WL目标光谱“按原样”测量（例如，没有简化，概括，假设等），以减少使用不确定和/或估计的目标固有的并发症。

公开(公告)号：US10134633B1

公开(公告)日：2018-11-20

申请号：US15791658

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Stan Tsai ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4757 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/417

Abstract: In a self-aligned contact (SAC) process, a sacrificial etch stop layer is embedded over source/drain regions, i.e., directly over an interlayer dielectric (IDL) disposed over source/drain regions to enable polishing of a nitride capping layer with respect to the interlayer dielectric. The sacrificial etch stop layer may comprise cobalt metal, and is adapted to be removed and replaced with additional ILD material after controlled polishing of the nitride capping layer.

公开(公告)号：US09812365B1

公开(公告)日：2017-11-07

申请号：US15286117

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Haigou Huang ,  Xusheng Wu ,  Ruilong Xie ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31056 ,  H01L21/31144 ,  H01L29/66545 ,  H01L29/66636

Abstract: One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.

公开(公告)号：US10593599B2

公开(公告)日：2020-03-17

申请号：US15914547

申请日：2018-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L27/088 ,  H01L29/45 ,  H01L29/06 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

公开(公告)号：US09865543B1

公开(公告)日：2018-01-09

申请号：US15416152

申请日：2017-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Haigou Huang ,  Stan Tsai ,  John H. Zhang ,  Xingzhao Shi ,  Tai Fong Chao

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/82 ,  H01L23/528 ,  H01L21/321 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L23/5283 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/53209

Abstract: A process for forming a conductive structure includes the formation of a self-aligned, inlaid conductive cap over a cobalt-based contact. The inlaid conductive cap is formed using a damascene process by depositing a conductive layer comprising tungsten or copper over a recessed cobalt-based contact, followed by a CMP step to remove excess portions of the conductive layer. The conductive cap can cooperate with a liner/barrier layer to form an effective barrier to cobalt migration and oxidation.