公开(公告)号：US09362284B2

公开(公告)日：2016-06-07

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L29/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

公开(公告)号：US08722485B1

公开(公告)日：2014-05-13

申请号：US13851810

申请日：2013-03-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Yiqun Liu ,  Tae-Hoon Kim ,  Seung Kim ,  Haiting Wang ,  Huang Liu

IPC: H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L21/823857 ,  H01L29/78

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供其上形成有牺牲氧化硅层的半导体衬底，形成在牺牲氧化硅层上的层间电介质层，以及在牺牲氧化硅层上形成的虚拟栅极结构， 所述层间介电层，去除所述虚拟栅极结构以在所述层间电介质层内形成开口，以及去除所述开口内的所述牺牲氧化硅层以在所述开口内露出所述半导体衬底。 该方法还包括以下步骤：在开口内的暴露的半导体衬底上热氧化形成氧化物层，对热形成的氧化物层进行去耦等离子体氧化处理，以及使用自饱和的湿蚀刻化学法蚀刻热成型的氧化物层。 此外，该方法包括在开口内的热形成的氧化物层上沉积高k电介质。

公开(公告)号：US09673039B2

公开(公告)日：2017-06-06

申请号：US14666787

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir Ray ,  Yiqun Liu ,  Jin Ping Liu ,  Fabio D'Addamio ,  Sandeep Gaan

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/28 ,  C23C16/30 ,  G11C11/22 ,  H01L29/51

CPC classification number: H01L21/02181 ,  C23C16/308 ,  G11C11/22 ,  H01L21/02189 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 Å thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

公开(公告)号：US09209186B1

公开(公告)日：2015-12-08

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。