公开(公告)号：US20210094281A1

公开(公告)日：2021-04-01

申请号：US16608061

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing NG ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Hang Ru Goy

IPC: B41J2/045

Abstract: In some examples, a circuit for use with a fluid ejection device includes a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the fluid ejection device. Each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

公开(公告)号：US09928912B2

公开(公告)日：2018-03-27

申请号：US15489272

申请日：2017-04-17

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: G11C11/34 ,  G11C16/08 ,  G11C8/04 ,  G11C16/24 ,  G11C8/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11514 ,  H01L29/423 ,  H01L29/78 ,  G11C8/12 ,  H01L27/11582

CPC classification number: G11C16/08 ,  G11C8/04 ,  G11C8/08 ,  G11C8/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11514 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/7841

Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

公开(公告)号：US11090926B2

公开(公告)日：2021-08-17

申请号：US16608061

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Hang Ru Goy

IPC: B41J2/045

Abstract: In some examples, a circuit for use with a fluid ejection device includes a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the fluid ejection device. Each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

公开(公告)号：US20200031116A1

公开(公告)日：2020-01-30

申请号：US16337837

申请日：2016-10-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: B41J2/045 ,  B41J2/175 ,  G11C7/12 ,  G11C11/4094

Abstract: In some examples, a control apparatus for a fluid ejection device includes a plurality of selectors controllable by an input control signal to produce signals for selecting respective nozzles of the fluid ejection device, where a first selector is responsive to the input control signal propagated over a first signal path to turn on a device in the first selector, and a second selector is responsive to the input control signal to perform a different task. A memory encoder is to select a memory location in the memory, the memory encoder responsive to the input control signal propagated over a second signal path to turn on a device in the memory encoder, where signal loading of the second signal path is isolated from signal loading of the first signal path.

公开(公告)号：US11285717B2

公开(公告)日：2022-03-29

申请号：US17016757

申请日：2020-09-10

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: B41J2/045 ,  G11C7/12 ,  B41J2/175 ,  G11C11/4094

Abstract: In some examples, a control apparatus for a fluid ejection device includes a plurality of selectors controllable by an input control signal to produce signals for selecting respective nozzles of the fluid ejection device, where a first selector is responsive to the input control signal propagated over a first signal path to turn on a device in the first selector, and a second selector is responsive to the input control signal to perform a different task. A memory encoder is to select a memory location in the memory, the memory encoder responsive to the input control signal propagated over a second signal path to turn on a device in the memory encoder, where signal loading of the second signal path is isolated from signal loading of the first signal path.

公开(公告)号：US10155379B2

公开(公告)日：2018-12-18

申请号：US15519310

申请日：2014-10-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy ,  Patrick Leonard ,  Shane O'Brien

IPC: B41J2/14 ,  B41J2/175 ,  B41J2/16

Abstract: A fluid ejection device including a printhead die having a plurality of layers, including a single metal layer, and having an integrated ink level sensor. The ink level sensor includes an ink chamber above the metal layer, a metal plate of a sense capacitor disposed in the metal layer, and a clearing resistor circuit disposed in the metal layer including four clearing resistors arranged in a surround-4 configuration about the metal plate and electrically connected in parallel between a voltage potential and ground, wherein adjacent ends of at least two clearing resistors are not directly connected to one another so as to leave a gap between the adjacent ends in the metal layer. A metal lead in the metal layer extends through the gap to the metal plate.

公开(公告)号：US10800168B2

公开(公告)日：2020-10-13

申请号：US16337837

申请日：2016-10-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: B41J2/045 ,  B41J2/175 ,  G11C11/4094 ,  G11C7/12

Abstract: In some examples, a control apparatus for a fluid ejection device includes a plurality of selectors controllable by an input control signal to produce signals for selecting respective nozzles of the fluid ejection device, where a first selector is responsive to the input control signal propagated over a first signal path to turn on a device in the first selector, and a second selector is responsive to the input control signal to perform a different task. A memory encoder is to select a memory location in the memory, the memory encoder responsive to the input control signal propagated over a second signal path to turn on a device in the memory encoder, where signal loading of the second signal path is isolated from signal loading of the first signal path.

公开(公告)号：US09773556B2

公开(公告)日：2017-09-26

申请号：US15114823

申请日：2014-01-31

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: G11C11/34 ,  G11C16/08 ,  G11C8/04 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C8/04 ,  G11C8/08 ,  G11C8/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11514 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/7841

Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

公开(公告)号：US10340011B2

公开(公告)日：2019-07-02

申请号：US15851413

申请日：2017-12-21

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: G11C16/08 ,  G11C8/04 ,  G11C16/24 ,  G11C8/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11514 ,  H01L29/423 ,  H01L29/78 ,  G11C8/12 ,  H01L27/11582

Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

公开(公告)号：US20170232743A1

公开(公告)日：2017-08-17

申请号：US15519310

申请日：2014-10-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy ,  Patrick Leonard ,  Shane O'Brien

IPC: B41J2/14 ,  B41J2/16

CPC classification number: B41J2/14072 ,  B41J2/14153 ,  B41J2/1601 ,  B41J2/164 ,  B41J2/175 ,  B41J2202/18

Abstract: A fluid ejection device including a printhead die having a plurality of layers, including a single metal layer, and having an integrated ink level sensor. The ink level sensor includes an ink chamber above the metal layer, a metal plate of a sense capacitor disposed in the metal layer, and a clearing resistor circuit disposed in the metal layer including four clearing resistors arranged in a surround-4 configuration about the metal plate and electrically connected in parallel between a voltage potential and ground, wherein adjacent ends of at least two clearing resistors are not directly connected to one another so as to leave a gap between the adjacent ends in the metal layer. A metal lead in the metal layer extends through the gap to the metal plate.