METHOD AND SYSTEM OF DESIGNING MEMRISTOR-BASED NAIVE BAYES CLASSIFIER AND CLASSIFIER

    公开(公告)号:US20230334824A1

    公开(公告)日:2023-10-19

    申请号:US17775591

    申请日:2021-05-07

    CPC classification number: G06V10/764 G06V10/955

    Abstract: A method and a system of designing a memristor-based naive Bayes classifier and a classifier belonging to the field of information technology are provided. The method includes: constructing a naive Bayes classifier including a memristor array of M rows by 2N columns, where M is the number of classification types, and N is the number of pixels in a picture; calculating the number hj,2i−1 of the pixel value of 0 and the number hj,2i of the pixel value of 1 in an ith pixel in the jth training sample, where j=1, 2, . . . , and M; and applying hj,2i−1 pulses to a memristor Rj,2i−1 in a jth row and a 2i−1th column to modulate the conductance of the memristor Rj,2i−1 and applying hj,2i pulses to a memristor Rj,2i in the jth row and a 2ith column to modulate the conductance of the memristor Rj,2i.

    NON-VOLATILE BOOLEAN LOGIC CIRCUIT BASED ON MEMRISTORS AND OPERATION METHOD THEREOF

    公开(公告)号:US20230170908A1

    公开(公告)日:2023-06-01

    申请号:US17794620

    申请日:2021-07-05

    CPC classification number: H03K19/1776 G11C13/004 G11C13/0069 H03K19/21

    Abstract: A non-volatile Boolean logic circuit based on memristors and an operation method, which performs logic operations on the input logic value P and/or the input logic value Q. The logic circuit includes: a controller, a memristor M1, a memristor M2 and a resistor. The controller sets the memristor M2 to a high resistance state before performing the logic operation. When performing the logic operation, a voltage A is applied to the memristor M1, a voltage B is applied to the memristor M2, a voltage C is applied to the resistor. The resistance state of the memristor M2 is the result of the logic operation. When a logic operation is performed on the logic value P and the logic value Q or only on the logic value Q, the controller further sets the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation.

    READ AND WRITE CIRCUIT OF THREE-DIMENSIONAL PHASE-CHANGE MEMORY

    公开(公告)号:US20220383951A1

    公开(公告)日:2022-12-01

    申请号:US17873186

    申请日:2022-07-26

    Abstract: A read and write circuit of a three-dimensional phase-change memory including an operation control circuit and a read and write operation circuit connected to each other. The operation control circuit is configured to load a correct operation pulse onto the read and write operation circuit. A read and write unit in the read and write operation circuit is connected to a memory cell and is configured to load the correct operation pulse onto the memory cell corresponding to the three-dimensional phase-change memory and to mirror the correct operation pulse to a mirror current. A bandgap reference source and a hysteresis comparator are connected to a mirror circuit branch. A feedback chopper circuit loop is connected across the memory cell and the mirror circuit branch and is configured to monitor a current flowing through the memory cell in real time.

    METHOD OF INDUCING CRYSTALLIZATION OF CHALCOGENIDE PHASE-CHANGE MATERIAL AND APPLICATION THEREOF

    公开(公告)号:US20220336743A1

    公开(公告)日:2022-10-20

    申请号:US17842800

    申请日:2022-06-17

    Abstract: The disclosure belongs to the field of microelectronics, and specifically, relates to a method of inducing crystallization of a chalcogenide phase-change material and application thereof. To be specific, a dielectric material is brought into contact with an interface of the chalcogenide phase-change material. The dielectric material is in an octahedral configuration, and the dielectric material provides a crystal nucleus growth center for the crystallization of the chalcogenide phase-change material at the interface between the two, so as to induce the phase-change material to accelerate the crystallization. The method is further applied in a phase-change memory cell. Among all the dielectric material layers in contact with the chalcogenide phase-change material layer, the dielectric material structure of at least one side of the dielectric material layer is an octahedral configuration.

    MULTI-LAYER PHASE CHANGE MATERIAL
    5.
    发明申请
    MULTI-LAYER PHASE CHANGE MATERIAL 有权
    多层相变材料

    公开(公告)号:US20130270503A1

    公开(公告)日:2013-10-17

    申请号:US13917681

    申请日:2013-06-14

    Abstract: A multi-layer phase change material, including: a multi-layer film structure. The multi-layer film structure includes a plurality of periodic units. The periodic units each includes a first single-layer film phase change material and a second single-layer film phase change material. The first single-layer film phase change material and the second single-layer film phase change material are alternately stacked. The first single-layer film phase change material includes chemical components that are different from chemical components included in the second single-layer film phase change material, or the first single-layer film phase change material includes chemical components that are the same as chemical components included in the second single-layer film phase change material and a percent composition of the chemical components included in the first single-layer film phase change material is different from a percent composition of the chemical components included in the second single-layer film phase change material.

    Abstract translation: 一种多层相变材料,包括:多层膜结构。 多层膜结构包括多个周期性单元。 周期性单元各自包括第一单层膜相变材料和第二单层膜相变材料。 第一单层膜相变材料和第二单层膜相变材料交替堆叠。 第一单层膜相变材料包括与第二单层膜相变材料中包含的化学成分不同的化学成分,或者第一单层膜相变材料包含与化学成分相同的化学成分 包含在第二单层膜相变材料中的包含在第一单层膜相变材料中的化学成分的组成百分比与第二单层膜相变中包含的化学成分的组成百分比不同 材料。

    CONVOLUTION OPERATION ACCELERATOR AND CONVOLUTION OPERATION METHOD

    公开(公告)号:US20250022490A1

    公开(公告)日:2025-01-16

    申请号:US18266610

    申请日:2022-04-20

    Abstract: The disclosure provides a convolution operation accelerator and a convolution operation method and belongs to the field of microelectronic devices. Input data of each word line may be subjected to a multiply-accumulate operation together with two upper and lower layers of convolution kernel units, so that natural sliding of the convolution kernel units in a y direction in two-dimensional input is achieved. The oblique bit lines and multiple copies of a convolution kernel in each layer of a non-volatile memory array may enable a multiplication operation between one piece of input data and convolution kernel data at different positions in the same convolution kernel. In this way, the natural sliding of the convolution kernel units in an x direction in the two-dimensional input is achieved.

    Cu-DOPED Sb-Te SYSTEM PHASE CHANGE MATERIAL, PHASE CHANGE MEMORY AND PREPARATION METHOD THEREOF

    公开(公告)号:US20230287253A1

    公开(公告)日:2023-09-14

    申请号:US17928932

    申请日:2021-12-22

    Abstract: A Cu-doped Sb2Te3 system phase change material, a phase change memory, and a preparation method thereof belonging to the technical field of micro-nano electronics are provided. A Sb—Te system phase change material is doped with Cu element to form Cu3Te2 bonds with both tetrahedral and octahedral structures in the case of local enrichment of Cu. The strongly bonded tetrahedral structure improves the amorphous stability and data retention capability of the Sb—Te system phase change material, and the octahedral structure of the crystal configuration improves the crystallization speed of the Sb—Te system phase change material. A phase change memory including the phase change material and a preparation method of the phase change material are also provided. Through the phase change material provided by the invention, both the speed and amorphous stability of the device are improved, and the comprehensive performance of the phase change memory is also enhanced.

    REVERSIBLE LOGIC CIRCUIT AND OPERATION METHOD THEREOF

    公开(公告)号:US20210218402A1

    公开(公告)日:2021-07-15

    申请号:US16965602

    申请日:2019-07-16

    Abstract: A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.

    REDUCED INSTRUCTION SET PROCESSOR BASED ON MEMRISTOR

    公开(公告)号:US20210117189A1

    公开(公告)日:2021-04-22

    申请号:US17054529

    申请日:2018-11-29

    Abstract: A reduced instruction set processor based on a memristor is provided. The memristor is a non-volatile device using a resistor to store “0” and “1” logic while implementing “implication logic” through applying a pair of voltages VCOND/VSET. Various data operations, logic operations, and arithmetic operations may be implemented based on the implication logic. The memristor is a computation and memory fusion device having great potential. A computer processor based on the memristor also becomes the research direction of the next-generation computer processor. The computer processor based on a memristor is designed according to the memory and computation fusion characteristic of the memristor. The processor is different from a traditional computer that must use a special memory and a calculator, and fuses computation and memory. Compared with a traditional computer, the speed, parallelism degree, and power consumption of the computer processor based on the memristor are greatly improved.

    PHASE-CHANGE MEMORY CELL
    10.
    发明申请

    公开(公告)号:US20200075848A1

    公开(公告)日:2020-03-05

    申请号:US16679355

    申请日:2019-11-11

    Abstract: A phase-change memory cell, including, in sequence in the following order: a first electrode layer, a switching layer comprising vanadium oxide (VOx) material, a phase-change material layer, and a second electrode layer. The switching layer is adapted to control the phase-change material layer to switch between a crystalline state and an amorphous state when a voltage is applied to the first electrode layer and the second electrode layer.

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