公开(公告)号：US20240213225A1

公开(公告)日：2024-06-27

申请号：US18601774

申请日：2024-03-11

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US20160358891A1

公开(公告)日：2016-12-08

申请号：US14778018

申请日：2014-12-15

Applicant: INTEL CORPORATION

Inventor： Christian GEISSLER ,  Thorsten MEYER

IPC: H01L25/065 ,  H01L25/00

Abstract: An apparatus including a first package coupled to a second package, wherein each of the first package and the second package has a first side and an opposite second side; a first die coupled to the first package; and a second die coupled to the second side of the second package, wherein the first package is coupled to the second package in a stacked arrangement such that the first side of the second package faces the second side of the first package. A method including coupling a first package to a second package in a stacked configuration, wherein the first package includes a first package substrate and a first die and the second package includes a second package substrate and a second die, wherein the second die is disposed on a side of the second package substrate opposite the first package substrate.

Abstract translation: 一种包括耦合到第二封装的第一封装的装置，其中所述第一封装和所述第二封装中的每一个具有第一侧和相对的第二侧; 耦合到所述第一封装的第一管芯; 以及耦合到所述第二封装的第二侧的第二裸片，其中所述第一封装以堆叠布置耦合到所述第二封装，使得所述第二封装的所述第一侧面向所述第一封装的第二侧。 一种包括以堆叠结构将第一封装耦合到第二封装的方法，其中所述第一封装包括第一封装衬底和第一管芯，所述第二封装包括第二封装衬底和第二管芯，其中所述第二管芯设置在 所述第二封装基板的与所述第一封装基板相对的一侧。

公开(公告)号：US20180286799A1

公开(公告)日：2018-10-04

申请号：US15997555

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Thorsten MEYER ,  Gerald OFNER ,  Andreas WOLTER ,  Georg SEIDEMANN ,  Sven ALBERS ,  Christian GEISSLER

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

公开(公告)号：US20220108976A1

公开(公告)日：2022-04-07

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.